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-rw-r--r--src/main/resources/top.cpp8
-rw-r--r--src/main/scala/chisel3/internal/firrtl/Emitter.scala4
2 files changed, 6 insertions, 6 deletions
diff --git a/src/main/resources/top.cpp b/src/main/resources/top.cpp
index 8bfe2a99..075d7085 100644
--- a/src/main/resources/top.cpp
+++ b/src/main/resources/top.cpp
@@ -44,10 +44,10 @@ int main(int argc, char** argv) {
top->reset = 0; // Deassert reset
}
if ((main_time % 10) == 1) {
- top->clk = 1; // Toggle clock
+ top->clock = 1; // Toggle clock
}
if ((main_time % 10) == 6) {
- top->clk = 0;
+ top->clock = 0;
}
top->eval(); // Evaluate model
#if VM_TRACE
@@ -69,10 +69,10 @@ int main(int argc, char** argv) {
vluint64_t end_time = main_time + 100;
while (main_time < end_time) {
if ((main_time % 10) == 1) {
- top->clk = 1; // Toggle clock
+ top->clock = 1; // Toggle clock
}
if ((main_time % 10) == 6) {
- top->clk = 0;
+ top->clock = 0;
}
top->eval(); // Evaluate model
#if VM_TRACE
diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
index 8849077d..f1908089 100644
--- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala
+++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
@@ -24,10 +24,10 @@ private class Emitter(circuit: Circuit) {
case e: DefMemPort[_] => s"${e.dir} mport ${e.name} = ${e.source.fullName(ctx)}[${e.index.fullName(ctx)}], ${e.clock.fullName(ctx)}"
case e: Connect => s"${e.loc.fullName(ctx)} <= ${e.exp.fullName(ctx)}"
case e: BulkConnect => s"${e.loc1.fullName(ctx)} <- ${e.loc2.fullName(ctx)}"
- case e: Stop => s"stop(${e.clk.fullName(ctx)}, UInt<1>(1), ${e.ret})"
+ case e: Stop => s"stop(${e.clock.fullName(ctx)}, UInt<1>(1), ${e.ret})"
case e: Printf =>
val (fmt, args) = e.pable.unpack(ctx)
- val printfArgs = Seq(e.clk.fullName(ctx), "UInt<1>(1)",
+ val printfArgs = Seq(e.clock.fullName(ctx), "UInt<1>(1)",
"\"" + printf.format(fmt) + "\"") ++ args
printfArgs mkString ("printf(", ", ", ")")
case e: DefInvalid => s"${e.arg.fullName(ctx)} is invalid"