summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
Diffstat (limited to 'src')
-rw-r--r--src/main/scala/chisel3/package.scala3
-rw-r--r--src/main/scala/chisel3/util/util.scala12
2 files changed, 12 insertions, 3 deletions
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 24deb64f..17ddd55a 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -165,9 +165,6 @@ package object chisel3 { // scalastyle:ignore package.object.name
val OUTPUT = chisel3.core.Direction.Output
val NODIR = chisel3.core.Direction.Unspecified
type ChiselException = chisel3.internal.ChiselException
- type ValidIO[+T <: Data] = chisel3.util.Valid[T]
- val ValidIO = chisel3.util.Valid
- val DecoupledIO = chisel3.util.Decoupled
class EnqIO[+T <: Data](gen: T) extends DecoupledIO(gen) {
def init(): Unit = {
diff --git a/src/main/scala/chisel3/util/util.scala b/src/main/scala/chisel3/util/util.scala
new file mode 100644
index 00000000..812af21c
--- /dev/null
+++ b/src/main/scala/chisel3/util/util.scala
@@ -0,0 +1,12 @@
+// See LICENSE for license details.
+
+package chisel3
+
+package object util {
+
+ /** Synonyms, moved from main package object - maintain scope. */
+ type ValidIO[+T <: Data] = chisel3.util.Valid[T]
+ val ValidIO = chisel3.util.Valid
+ val DecoupledIO = chisel3.util.Decoupled
+
+}