diff options
Diffstat (limited to 'src')
20 files changed, 34 insertions, 35 deletions
diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala index 646fc84e..aad15f60 100644 --- a/src/main/scala/chisel3/compatibility.scala +++ b/src/main/scala/chisel3/compatibility.scala @@ -4,7 +4,7 @@ // moving to the more standard package naming convention chisel3 (lowercase c). package object Chisel { // scalastyle:ignore package.object.name - implicit val defaultCompileOptions = chisel3.ExplicitCompileOptions.NotStrict + implicit val defaultCompileOptions = chisel3.core.ExplicitCompileOptions.NotStrict type Direction = chisel3.core.Direction val INPUT = chisel3.core.Direction.Input val OUTPUT = chisel3.core.Direction.Output diff --git a/src/main/scala/chisel3/testers/BasicTester.scala b/src/main/scala/chisel3/testers/BasicTester.scala index 93bb4c33..bd7d4027 100644 --- a/src/main/scala/chisel3/testers/BasicTester.scala +++ b/src/main/scala/chisel3/testers/BasicTester.scala @@ -9,7 +9,7 @@ import internal._ import internal.Builder.pushCommand import internal.firrtl._ import internal.sourceinfo.SourceInfo -//import chisel3.ExplicitCompileOptions.NotStrict +//import chisel3.core.ExplicitCompileOptions.NotStrict class BasicTester extends Module() { // The testbench has no IOs, rather it should communicate using printf, assert, and stop. diff --git a/src/main/scala/chisel3/util/Arbiter.scala b/src/main/scala/chisel3/util/Arbiter.scala index adeb1b34..89bb644a 100644 --- a/src/main/scala/chisel3/util/Arbiter.scala +++ b/src/main/scala/chisel3/util/Arbiter.scala @@ -6,7 +6,8 @@ package chisel3.util import chisel3._ -//import chisel3.ExplicitCompileOptions.NotStrict +// TODO: remove this once we have CompileOptions threaded through the macro system. +import chisel3.core.ExplicitCompileOptions.NotStrict /** IO bundle definition for an Arbiter, which takes some number of ready-valid inputs and outputs * (selects) at most one. diff --git a/src/main/scala/chisel3/util/Counter.scala b/src/main/scala/chisel3/util/Counter.scala index b22cfa7b..ba66d667 100644 --- a/src/main/scala/chisel3/util/Counter.scala +++ b/src/main/scala/chisel3/util/Counter.scala @@ -3,7 +3,7 @@ package chisel3.util import chisel3._ -//import chisel3.ExplicitCompileOptions.Strict +//import chisel3.core.ExplicitCompileOptions.Strict /** A counter module * diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala index 947d02f8..a0cbf4f7 100644 --- a/src/main/scala/chisel3/util/Decoupled.scala +++ b/src/main/scala/chisel3/util/Decoupled.scala @@ -6,7 +6,8 @@ package chisel3.util import chisel3._ -//import chisel3.ExplicitCompileOptions.NotStrict +// TODO: remove this once we have CompileOptions threaded through the macro system. +import chisel3.core.ExplicitCompileOptions.NotStrict /** An I/O Bundle containing 'valid' and 'ready' signals that handshake * the transfer of data stored in the 'bits' subfield. diff --git a/src/main/scala/chisel3/util/LFSR.scala b/src/main/scala/chisel3/util/LFSR.scala index 95b4da81..fedbf194 100644 --- a/src/main/scala/chisel3/util/LFSR.scala +++ b/src/main/scala/chisel3/util/LFSR.scala @@ -6,7 +6,7 @@ package chisel3.util import chisel3._ -//import chisel3.ExplicitCompileOptions.Strict +//import chisel3.core.ExplicitCompileOptions.Strict // scalastyle:off magic.number object LFSR16 { diff --git a/src/main/scala/chisel3/util/Reg.scala b/src/main/scala/chisel3/util/Reg.scala index fcfc9ac5..713a3b2e 100644 --- a/src/main/scala/chisel3/util/Reg.scala +++ b/src/main/scala/chisel3/util/Reg.scala @@ -3,7 +3,8 @@ package chisel3.util import chisel3._ -//import chisel3.ExplicitCompileOptions.NotStrict +// TODO: remove this once we have CompileOptions threaded through the macro system. +import chisel3.core.ExplicitCompileOptions.NotStrict object RegNext { /** Returns a register with the specified next and no reset initialization. diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala index 67be7648..3d153a2a 100644 --- a/src/main/scala/chisel3/util/Valid.scala +++ b/src/main/scala/chisel3/util/Valid.scala @@ -6,7 +6,8 @@ package chisel3.util import chisel3._ -//import chisel3.ExplicitCompileOptions.NotStrict +// TODO: remove this once we have CompileOptions threaded through the macro system. +import chisel3.core.ExplicitCompileOptions.NotStrict /** An Bundle containing data and a signal determining if it is valid */ class Valid[+T <: Data](gen: T) extends Bundle diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala index 465dec4e..344754e1 100644 --- a/src/test/scala/chiselTests/BlackBox.scala +++ b/src/test/scala/chiselTests/BlackBox.scala @@ -8,7 +8,7 @@ import org.scalatest._ import chisel3._ import chisel3.testers.BasicTester import chisel3.util._ -//import chisel3.ExplicitCompileOptions.Strict +//import chisel3.core.ExplicitCompileOptions.Strict class BlackBoxInverter extends BlackBox { val io = IO(new Bundle() { diff --git a/src/test/scala/chiselTests/BundleWire.scala b/src/test/scala/chiselTests/BundleWire.scala index 07360c34..53d46e93 100644 --- a/src/test/scala/chiselTests/BundleWire.scala +++ b/src/test/scala/chiselTests/BundleWire.scala @@ -5,7 +5,7 @@ import chisel3._ import org.scalatest._ import org.scalatest.prop._ import chisel3.testers.BasicTester -//import chisel3.ExplicitCompileOptions.Strict +//import chisel3.core.ExplicitCompileOptions.Strict class Coord extends Bundle { val x = UInt.width( 32) diff --git a/src/test/scala/chiselTests/CompileOptionsTest.scala b/src/test/scala/chiselTests/CompileOptionsTest.scala index 508c0849..83077544 100644 --- a/src/test/scala/chiselTests/CompileOptionsTest.scala +++ b/src/test/scala/chiselTests/CompileOptionsTest.scala @@ -5,17 +5,18 @@ package chiselTests import org.scalatest._ import chisel3._ import chisel3.core.Binding.BindingException -import chisel3.ExplicitImplicitCompileOptions +import chisel3.core.ExplicitCompileOptions import chisel3.testers.BasicTester +import chisel3.core.CompileOptions class CompileOptionsSpec extends ChiselFlatSpec { - abstract class StrictModule extends Module()(chisel3.ExplicitCompileOptions.Strict) - abstract class NotStrictModule extends Module()(chisel3.ExplicitCompileOptions.NotStrict) + abstract class StrictModule extends Module()(chisel3.core.ExplicitCompileOptions.Strict) + abstract class NotStrictModule extends Module()(chisel3.core.ExplicitCompileOptions.NotStrict) // Generate a set of options that do not have requireIOWrap enabled, in order to // ensure its definition comes from the implicit options passed to the Module constructor. - object StrictWithoutIOWrap extends ExplicitImplicitCompileOptions { + object StrictWithoutIOWrap extends CompileOptions { val connectFieldsMustMatch = true val declaredTypeMustBeUnbound = true val requireIOWrap = false @@ -35,7 +36,7 @@ class CompileOptionsSpec extends ChiselFlatSpec { "A Module with missing bundle fields when compiled with implicit Strict.CompileOption " should "throw an exception" in { a [ChiselException] should be thrownBy { - import chisel3.ExplicitCompileOptions.Strict + import chisel3.core.ExplicitCompileOptions.Strict class ConnectFieldMismatchModule extends Module { val io = IO(new Bundle { @@ -49,7 +50,7 @@ class CompileOptionsSpec extends ChiselFlatSpec { } "A Module with missing bundle fields when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in { - import chisel3.ExplicitCompileOptions.NotStrict + import chisel3.core.ExplicitCompileOptions.NotStrict class ConnectFieldMismatchModule extends Module { val io = IO(new Bundle { @@ -63,7 +64,7 @@ class CompileOptionsSpec extends ChiselFlatSpec { "A Module in which a Reg is created with a bound type when compiled with implicit Strict.CompileOption " should "throw an exception" in { a [BindingException] should be thrownBy { - import chisel3.ExplicitCompileOptions.Strict + import chisel3.core.ExplicitCompileOptions.Strict class CreateRegFromBoundTypeModule extends Module { val io = IO(new Bundle { @@ -77,7 +78,7 @@ class CompileOptionsSpec extends ChiselFlatSpec { } "A Module in which a Reg is created with a bound type when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in { - import chisel3.ExplicitCompileOptions.NotStrict + import chisel3.core.ExplicitCompileOptions.NotStrict class CreateRegFromBoundTypeModule extends Module { val io = IO(new Bundle { @@ -90,7 +91,7 @@ class CompileOptionsSpec extends ChiselFlatSpec { } "A Module with wrapped IO when compiled with implicit Strict.CompileOption " should "not throw an exception" in { - import chisel3.ExplicitCompileOptions.Strict + import chisel3.core.ExplicitCompileOptions.Strict class RequireIOWrapModule extends Module { val io = IO(new Bundle { @@ -103,7 +104,7 @@ class CompileOptionsSpec extends ChiselFlatSpec { } "A Module with unwrapped IO when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in { - import chisel3.ExplicitCompileOptions.NotStrict + import chisel3.core.ExplicitCompileOptions.NotStrict class RequireIOWrapModule extends Module { val io = new Bundle { @@ -117,7 +118,7 @@ class CompileOptionsSpec extends ChiselFlatSpec { "A Module with unwrapped IO when compiled with implicit Strict.CompileOption " should "throw an exception" in { a [BindingException] should be thrownBy { - import chisel3.ExplicitCompileOptions.Strict + import chisel3.core.ExplicitCompileOptions.Strict class RequireIOWrapModule extends Module { val io = new Bundle { @@ -134,7 +135,7 @@ class CompileOptionsSpec extends ChiselFlatSpec { "A Module connecting output as source to input as sink when compiled with implicit Strict.CompileOption " should "throw an exception" in { a [ChiselException] should be thrownBy { - import chisel3.ExplicitCompileOptions.Strict + import chisel3.core.ExplicitCompileOptions.Strict class SimpleModule extends Module { val io = IO(new Bundle { @@ -151,7 +152,7 @@ class CompileOptionsSpec extends ChiselFlatSpec { } "A Module connecting output as source to input as sink when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in { - import chisel3.ExplicitCompileOptions.NotStrict + import chisel3.core.ExplicitCompileOptions.NotStrict class SimpleModule extends Module { val io = IO(new Bundle { @@ -170,7 +171,7 @@ class CompileOptionsSpec extends ChiselFlatSpec { a [ChiselException] should be thrownBy { // Verify we can suppress the inclusion of default compileOptions import Chisel.{defaultCompileOptions => _, _} - import chisel3.ExplicitCompileOptions.Strict + import chisel3.core.ExplicitCompileOptions.Strict class SimpleModule extends Module { val io = IO(new Bundle { @@ -191,7 +192,7 @@ class CompileOptionsSpec extends ChiselFlatSpec { } "A Module with directionless connections when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in { - import chisel3.ExplicitCompileOptions.NotStrict + import chisel3.core.ExplicitCompileOptions.NotStrict class SimpleModule extends Module { val io = IO(new Bundle { @@ -258,7 +259,7 @@ class CompileOptionsSpec extends ChiselFlatSpec { object StrictNotIOWrap { - implicit object CompileOptions extends ExplicitImplicitCompileOptions { + implicit object CompileOptions extends CompileOptions { val connectFieldsMustMatch = true val declaredTypeMustBeUnbound = true val requireIOWrap = false diff --git a/src/test/scala/chiselTests/SIntOps.scala b/src/test/scala/chiselTests/SIntOps.scala index 418318fb..392c4803 100644 --- a/src/test/scala/chiselTests/SIntOps.scala +++ b/src/test/scala/chiselTests/SIntOps.scala @@ -4,7 +4,6 @@ package chiselTests import chisel3._ import chisel3.testers.BasicTester -//import chisel3.ExplicitCompileOptions.NotStrict class SIntOps extends Module { val io = IO(new Bundle { diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala index 937f1978..a72af928 100644 --- a/src/test/scala/chiselTests/Stack.scala +++ b/src/test/scala/chiselTests/Stack.scala @@ -6,7 +6,6 @@ import scala.collection.mutable.Stack import chisel3._ import chisel3.util._ -//import chisel3.ExplicitCompileOptions.NotStrict class ChiselStack(val depth: Int) extends Module { val io = IO(new Bundle { diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala index 5ff1aa31..66a06435 100644 --- a/src/test/scala/chiselTests/Tbl.scala +++ b/src/test/scala/chiselTests/Tbl.scala @@ -8,7 +8,6 @@ import org.scalatest.prop._ import chisel3._ import chisel3.testers.BasicTester import chisel3.util._ -//import chisel3.ExplicitCompileOptions.NotStrict class Tbl(w: Int, n: Int) extends Module { val io = IO(new Bundle { diff --git a/src/test/scala/chiselTests/TesterDriverSpec.scala b/src/test/scala/chiselTests/TesterDriverSpec.scala index a5351763..b2e811d9 100644 --- a/src/test/scala/chiselTests/TesterDriverSpec.scala +++ b/src/test/scala/chiselTests/TesterDriverSpec.scala @@ -5,7 +5,7 @@ package chiselTests import chisel3._ import chisel3.testers.BasicTester import chisel3.util._ -//import chisel3.ExplicitCompileOptions.Strict +//import chisel3.core.ExplicitCompileOptions.Strict /** Extend BasicTester with a simple circuit and finish method. TesterDriver will call the * finish method after the FinishTester's constructor has completed, which will alter the diff --git a/src/test/scala/chiselTests/UIntOps.scala b/src/test/scala/chiselTests/UIntOps.scala index d80d6f17..ad5aecd8 100644 --- a/src/test/scala/chiselTests/UIntOps.scala +++ b/src/test/scala/chiselTests/UIntOps.scala @@ -5,7 +5,6 @@ package chiselTests import chisel3._ import org.scalatest._ import chisel3.testers.BasicTester -//import chisel3.ExplicitCompileOptions.NotStrict class UIntOps extends Module { val io = IO(new Bundle { diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala index a7dd975f..c5447610 100644 --- a/src/test/scala/chiselTests/Vec.scala +++ b/src/test/scala/chiselTests/Vec.scala @@ -8,7 +8,7 @@ import org.scalatest.prop._ import chisel3._ import chisel3.testers.BasicTester import chisel3.util._ -//import chisel3.ExplicitCompileOptions.Strict +//import chisel3.core.ExplicitCompileOptions.Strict class ValueTester(w: Int, values: List[Int]) extends BasicTester { val v = Vec(values.map(UInt(_, width = w))) // TODO: does this need a Wire? Why no error? diff --git a/src/test/scala/chiselTests/VectorPacketIO.scala b/src/test/scala/chiselTests/VectorPacketIO.scala index 221fd6d8..b8e3a154 100644 --- a/src/test/scala/chiselTests/VectorPacketIO.scala +++ b/src/test/scala/chiselTests/VectorPacketIO.scala @@ -5,7 +5,6 @@ package chiselTests import chisel3._ import chisel3.testers.BasicTester import chisel3.util._ -//import chisel3.ExplicitCompileOptions.NotStrict /** * This test used to fail when assignment statements were diff --git a/src/test/scala/chiselTests/VendingMachine.scala b/src/test/scala/chiselTests/VendingMachine.scala index 5f65659b..00b1e7de 100644 --- a/src/test/scala/chiselTests/VendingMachine.scala +++ b/src/test/scala/chiselTests/VendingMachine.scala @@ -4,7 +4,6 @@ package chiselTests import chisel3._ import chisel3.util._ -//import chisel3.ExplicitCompileOptions.NotStrict class VendingMachine extends Module { val io = IO(new Bundle { diff --git a/src/test/scala/chiselTests/When.scala b/src/test/scala/chiselTests/When.scala index 0183c29b..6dc2dbac 100644 --- a/src/test/scala/chiselTests/When.scala +++ b/src/test/scala/chiselTests/When.scala @@ -7,7 +7,7 @@ import org.scalatest._ import chisel3._ import chisel3.testers.BasicTester import chisel3.util._ -//import chisel3.ExplicitCompileOptions.Strict +//import chisel3.core.ExplicitCompileOptions.Strict class WhenTester() extends BasicTester { val cnt = Counter(4) |