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Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/Chisel/Core.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/Chisel/Core.scala b/src/main/scala/Chisel/Core.scala index 64c0e0f6..37f1f35a 100644 --- a/src/main/scala/Chisel/Core.scala +++ b/src/main/scala/Chisel/Core.scala @@ -936,7 +936,7 @@ object Bundle { class Bundle(dirArg: Direction = NO_DIR) extends Aggregate(dirArg) { def toPorts: Seq[Port] = - elements.map(_._2.toPort).toSeq + elements.map(_._2.toPort).toSeq.reverse def toType: BundleType = BundleType(this.toPorts, isFlipVar) |