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Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/Chisel/Driver.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/Chisel/Driver.scala b/src/main/scala/Chisel/Driver.scala index 830bc005..d5952834 100644 --- a/src/main/scala/Chisel/Driver.scala +++ b/src/main/scala/Chisel/Driver.scala @@ -110,12 +110,12 @@ object Driver extends BackendCompilationUtilities { */ def elaborate[T <: Module](gen: () => T): Circuit = Builder.build(Module(gen())) - def emit[T <: Module](gen: () => T): String = elaborate(gen).emit + def emit[T <: Module](gen: () => T): String = Emitter.emit(elaborate(gen)) def dumpFirrtl(ir: Circuit, optName: Option[File]): File = { val f = optName.getOrElse(new File(ir.name + ".fir")) val w = new FileWriter(f) - w.write(ir.emit) + w.write(Emitter.emit(ir)) w.close() f } |