1 files changed, 6 insertions, 4 deletions
diff --git a/src/main/scala/chisel3/testers/TesterDriver.scala b/src/main/scala/chisel3/testers/TesterDriver.scala
index e4bdda0b..df26e3c3 100644
--- a/src/main/scala/chisel3/testers/TesterDriver.scala
+++ b/src/main/scala/chisel3/testers/TesterDriver.scala
@@ -7,6 +7,7 @@ import java.io._
 
 import chisel3.experimental.RunFirrtlTransform
 import firrtl.{Driver => _, _}
+import firrtl.transforms.BlackBoxSourceHelper.writeResourceToDirectory
 
 object TesterDriver extends BackendCompilationUtilities {
 
@@ -31,11 +32,12 @@ object TesterDriver extends BackendCompilationUtilities {
     // Copy CPP harness and other Verilog sources from resources into files
     val cppHarness =  new File(path, "top.cpp")
     copyResourceToFile("/chisel3/top.cpp", cppHarness)
+    // NOTE: firrtl.Driver.execute() may end up copying these same resources in its BlackBoxSourceHelper code.
+    // As long as the same names are used for the output files, and we avoid including duplicate files
+    //  in BackendCompilationUtilities.verilogToCpp(), we should be okay.
+    // To that end, we use the same method to write the resource to the target directory.
     val additionalVFiles = additionalVResources.map((name: String) => {
-      val mangledResourceName = name.replace("/", "_")
-      val out = new File(path, mangledResourceName)
-      copyResourceToFile(name, out)
-      out
+      writeResourceToDirectory(name, path)
     })
 
     // Compile firrtl