diff options
Diffstat (limited to 'src')
9 files changed, 42 insertions, 17 deletions
diff --git a/src/main/scala/chisel3/stage/phases/AddImplicitOutputAnnotationFile.scala b/src/main/scala/chisel3/stage/phases/AddImplicitOutputAnnotationFile.scala index de251ab6..c7761d24 100644 --- a/src/main/scala/chisel3/stage/phases/AddImplicitOutputAnnotationFile.scala +++ b/src/main/scala/chisel3/stage/phases/AddImplicitOutputAnnotationFile.scala @@ -4,12 +4,14 @@ package chisel3.stage.phases import chisel3.stage.ChiselCircuitAnnotation import firrtl.AnnotationSeq -import firrtl.options.{OutputAnnotationFileAnnotation, Phase} +import firrtl.options.{OutputAnnotationFileAnnotation, Phase, PreservesAll} /** Adds an [[firrtl.options.OutputAnnotationFileAnnotation]] if one does not exist. This replicates old behavior where * an output annotation file was always written. */ -class AddImplicitOutputAnnotationFile extends Phase { +class AddImplicitOutputAnnotationFile extends Phase with PreservesAll[Phase] { + + override val prerequisites = Seq(classOf[Elaborate]) def transform(annotations: AnnotationSeq): AnnotationSeq = annotations .collectFirst{ case _: OutputAnnotationFileAnnotation => annotations } diff --git a/src/main/scala/chisel3/stage/phases/AddImplicitOutputFile.scala b/src/main/scala/chisel3/stage/phases/AddImplicitOutputFile.scala index 4a4dac72..cf808d26 100644 --- a/src/main/scala/chisel3/stage/phases/AddImplicitOutputFile.scala +++ b/src/main/scala/chisel3/stage/phases/AddImplicitOutputFile.scala @@ -3,14 +3,16 @@ package chisel3.stage.phases import firrtl.AnnotationSeq -import firrtl.options.Phase +import firrtl.options.{Phase, PreservesAll} import chisel3.stage.{ChiselCircuitAnnotation, ChiselOutputFileAnnotation} /** Add a output file for a Chisel circuit, derived from the top module in the circuit, if no * [[ChiselOutputFileAnnotation]] already exists. */ -class AddImplicitOutputFile extends Phase { +class AddImplicitOutputFile extends Phase with PreservesAll[Phase] { + + override val prerequisites = Seq(classOf[Elaborate]) def transform(annotations: AnnotationSeq): AnnotationSeq = annotations.collectFirst{ case _: ChiselOutputFileAnnotation => annotations }.getOrElse{ diff --git a/src/main/scala/chisel3/stage/phases/Checks.scala b/src/main/scala/chisel3/stage/phases/Checks.scala index e2606019..879379ce 100644 --- a/src/main/scala/chisel3/stage/phases/Checks.scala +++ b/src/main/scala/chisel3/stage/phases/Checks.scala @@ -6,12 +6,14 @@ import chisel3.stage.{ChiselOutputFileAnnotation, NoRunFirrtlCompilerAnnotation, import firrtl.AnnotationSeq import firrtl.annotations.Annotation -import firrtl.options.{OptionsException, Phase} +import firrtl.options.{OptionsException, Phase, PreservesAll} /** Sanity checks an [[firrtl.AnnotationSeq]] before running the main [[firrtl.options.Phase]]s of * [[chisel3.stage.ChiselStage]]. */ -class Checks extends Phase { +class Checks extends Phase with PreservesAll[Phase] { + + override val dependents = Seq(classOf[Elaborate]) def transform(annotations: AnnotationSeq): AnnotationSeq = { val noF, st, outF = collection.mutable.ListBuffer[Annotation]() diff --git a/src/main/scala/chisel3/stage/phases/Convert.scala b/src/main/scala/chisel3/stage/phases/Convert.scala index f08367c6..ac477330 100644 --- a/src/main/scala/chisel3/stage/phases/Convert.scala +++ b/src/main/scala/chisel3/stage/phases/Convert.scala @@ -6,7 +6,7 @@ import chisel3.experimental.RunFirrtlTransform import chisel3.internal.firrtl.Converter import chisel3.stage.ChiselCircuitAnnotation import firrtl.{AnnotationSeq, Transform} -import firrtl.options.Phase +import firrtl.options.{Phase, PreservesAll} import firrtl.stage.{FirrtlCircuitAnnotation, RunFirrtlTransformAnnotation} /** This prepares a [[ChiselCircuitAnnotation]] for compilation with FIRRTL. This does three things: @@ -14,7 +14,9 @@ import firrtl.stage.{FirrtlCircuitAnnotation, RunFirrtlTransformAnnotation} * - Extracts all [[firrtl.annotations.Annotation]]s from the [[chisel3.internal.firrtl.Circuit]] * - Generates any needed [[RunFirrtlTransformAnnotation]]s from extracted [[firrtl.annotations.Annotation]]s */ -class Convert extends Phase { +class Convert extends Phase with PreservesAll[Phase] { + + override val prerequisites = Seq(classOf[Elaborate]) def transform(annotations: AnnotationSeq): AnnotationSeq = annotations.flatMap { case a: ChiselCircuitAnnotation => diff --git a/src/main/scala/chisel3/stage/phases/DriverCompatibility.scala b/src/main/scala/chisel3/stage/phases/DriverCompatibility.scala index b7674aa1..0af796a4 100644 --- a/src/main/scala/chisel3/stage/phases/DriverCompatibility.scala +++ b/src/main/scala/chisel3/stage/phases/DriverCompatibility.scala @@ -4,7 +4,7 @@ package chisel3.stage.phases import firrtl.{AnnotationSeq, ExecutionOptionsManager, HasFirrtlOptions} import firrtl.annotations.NoTargetAnnotation -import firrtl.options.{OutputAnnotationFileAnnotation, Phase} +import firrtl.options.{OutputAnnotationFileAnnotation, Phase, PreservesAll} import firrtl.stage.{FirrtlCircuitAnnotation, RunFirrtlTransformAnnotation} import firrtl.stage.phases.DriverCompatibility.TopNameAnnotation @@ -25,7 +25,9 @@ object DriverCompatibility { * the correct behavior before a circuit has been elaborated. * @note the output suffix is unspecified and will be set by the underlying [[firrtl.EmittedComponent]] */ - private[chisel3] class AddImplicitOutputFile extends Phase { +private [chisel3] class AddImplicitOutputFile extends Phase with PreservesAll[Phase] { + + override val dependents = Seq( classOf[firrtl.stage.phases.DriverCompatibility.AddImplicitOutputFile] ) def transform(annotations: AnnotationSeq): AnnotationSeq = { val hasOutputFile = annotations @@ -47,7 +49,7 @@ object DriverCompatibility { * correct behavior before a circuit has been elaborated. * @note the output suffix is unspecified and will be set by [[firrtl.options.phases.WriteOutputAnnotations]] */ - private[chisel3] class AddImplicitOutputAnnotationFile extends Phase { + private[chisel3] class AddImplicitOutputAnnotationFile extends Phase with PreservesAll[Phase] { def transform(annotations: AnnotationSeq): AnnotationSeq = annotations diff --git a/src/main/scala/chisel3/stage/phases/Elaborate.scala b/src/main/scala/chisel3/stage/phases/Elaborate.scala index 2ec5f92c..150eacbe 100644 --- a/src/main/scala/chisel3/stage/phases/Elaborate.scala +++ b/src/main/scala/chisel3/stage/phases/Elaborate.scala @@ -9,11 +9,11 @@ import chisel3.internal.ErrorLog import chisel3.stage.{ChiselGeneratorAnnotation, ChiselOptions} import firrtl.AnnotationSeq import firrtl.options.Viewer.view -import firrtl.options.{OptionsException, Phase} +import firrtl.options.{OptionsException, Phase, PreservesAll} /** Elaborate all [[chisel3.stage.ChiselGeneratorAnnotation]]s into [[chisel3.stage.ChiselCircuitAnnotation]]s. */ -class Elaborate extends Phase { +class Elaborate extends Phase with PreservesAll[Phase] { /** * @todo Change this to print to STDERR (`Console.err.println`) diff --git a/src/main/scala/chisel3/stage/phases/Emitter.scala b/src/main/scala/chisel3/stage/phases/Emitter.scala index 1bdb9f8d..a0530bd2 100644 --- a/src/main/scala/chisel3/stage/phases/Emitter.scala +++ b/src/main/scala/chisel3/stage/phases/Emitter.scala @@ -24,6 +24,17 @@ import java.io.{File, FileWriter} */ class Emitter extends Phase { + override val prerequisites = + Seq( classOf[Elaborate], + classOf[AddImplicitOutputFile], + classOf[AddImplicitOutputAnnotationFile], + classOf[MaybeAspectPhase] ) + + override def invalidates(phase: Phase): Boolean = phase match { + case _: Elaborate => true + case _ => false + } + def transform(annotations: AnnotationSeq): AnnotationSeq = { val copts = view[ChiselOptions](annotations) val sopts = view[StageOptions](annotations) diff --git a/src/main/scala/chisel3/stage/phases/MaybeAspectPhase.scala b/src/main/scala/chisel3/stage/phases/MaybeAspectPhase.scala index 3e8b8feb..a69bc352 100644 --- a/src/main/scala/chisel3/stage/phases/MaybeAspectPhase.scala +++ b/src/main/scala/chisel3/stage/phases/MaybeAspectPhase.scala @@ -4,11 +4,13 @@ package chisel3.stage.phases import chisel3.aop.Aspect import firrtl.AnnotationSeq -import firrtl.options.Phase +import firrtl.options.{Phase, PreservesAll} /** Run [[AspectPhase]] if a [[chisel3.aop.Aspect]] is present. */ -class MaybeAspectPhase extends Phase { +class MaybeAspectPhase extends Phase with PreservesAll[Phase] { + + override val prerequisites = Seq(classOf[Elaborate]) def transform(annotations: AnnotationSeq): AnnotationSeq = { if(annotations.collectFirst { case a: Aspect[_] => annotations }.isDefined) { diff --git a/src/main/scala/chisel3/stage/phases/MaybeFirrtlStage.scala b/src/main/scala/chisel3/stage/phases/MaybeFirrtlStage.scala index f830c182..838b6819 100644 --- a/src/main/scala/chisel3/stage/phases/MaybeFirrtlStage.scala +++ b/src/main/scala/chisel3/stage/phases/MaybeFirrtlStage.scala @@ -5,12 +5,14 @@ package chisel3.stage.phases import chisel3.stage.NoRunFirrtlCompilerAnnotation import firrtl.AnnotationSeq -import firrtl.options.Phase +import firrtl.options.{Phase, PreservesAll} import firrtl.stage.FirrtlStage /** Run [[firrtl.stage.FirrtlStage]] if a [[chisel3.stage.NoRunFirrtlCompilerAnnotation]] is not present. */ -class MaybeFirrtlStage extends Phase { +class MaybeFirrtlStage extends Phase with PreservesAll[Phase] { + + override val prerequisites = Seq(classOf[Convert]) def transform(annotations: AnnotationSeq): AnnotationSeq = annotations .collectFirst { case NoRunFirrtlCompilerAnnotation => annotations } |