3 files changed, 15 insertions, 17 deletions
diff --git a/src/main/scala/Chisel/Core.scala b/src/main/scala/Chisel/Core.scala
index f2857f7c..64c0e0f6 100644
--- a/src/main/scala/Chisel/Core.scala
+++ b/src/main/scala/Chisel/Core.scala
@@ -439,7 +439,7 @@ class SeqMem[T <: Data](t: T, n: Int) {
 object Vec {
   def apply[T <: Data](gen: T, n: Int): Vec[T] = 
     new Vec((0 until n).map(i => gen.cloneType))
-  def apply[T <: Data](elts: Iterable[T]): Vec[T] = {
+  def apply[T <: Data](elts: Seq[T]): Vec[T] = {
     val vec = new Vec[T](elts.map(e => elts.head.cloneType))
     if (vec.isReg)
       throw new Exception("Vec of Reg Deprecated.")
@@ -461,7 +461,7 @@ abstract class Aggregate(dirArg: Direction) extends Data(dirArg) {
   def cloneTypeWidth(width: Int): this.type = cloneType
 }
 
-class Vec[T <: Data](elts: Iterable[T], dirArg: Direction = NO_DIR) extends Aggregate(dirArg) with VecLike[T] {
+class Vec[T <: Data](elts: Seq[T], dirArg: Direction = NO_DIR) extends Aggregate(dirArg) with VecLike[T] {
   private val self = elts.toIndexedSeq
   private lazy val elt0 = elts.head
 
@@ -469,11 +469,11 @@ class Vec[T <: Data](elts: Iterable[T], dirArg: Direction = NO_DIR) extends Aggr
     for ((e, i) <- self zipWithIndex)
       setIndexForId(cid, e.cid, i)
 
-  def <> (that: Iterable[T]): Unit =
+  def <> (that: Seq[T]): Unit =
     for ((a, b) <- this zip that)
       a <> b
 
-  def := (that: Iterable[T]): Unit =
+  def := (that: Seq[T]): Unit =
     for ((a, b) <- this zip that)
       a := b
 
diff --git a/src/main/scala/Chisel/Log2.scala b/src/main/scala/Chisel/Log2.scala
index fe1c1372..01b081ef 100644
--- a/src/main/scala/Chisel/Log2.scala
+++ b/src/main/scala/Chisel/Log2.scala
@@ -30,6 +30,6 @@ object OHToUInt {
 }
 
 object PriorityEncoder {
-  def apply(in: Iterable[Bool]): UInt = PriorityMux(in, (0 until in.size).map(UInt(_)))
+  def apply(in: Seq[Bool]): UInt = PriorityMux(in, (0 until in.size).map(UInt(_)))
   def apply(in: Bits): UInt = apply(in.toBools)
 }
diff --git a/src/main/scala/Chisel/utils.scala b/src/main/scala/Chisel/utils.scala
index 7f9811fd..c2e88bd2 100644
--- a/src/main/scala/Chisel/utils.scala
+++ b/src/main/scala/Chisel/utils.scala
@@ -84,18 +84,16 @@ object RegEnable
   */
 object Mux1H
 {
-  def apply[T <: Data](sel: Iterable[Bool], in: Iterable[T]): T = {
-    if (in.tail.isEmpty) in.head
+  def apply[T <: Data](sel: Seq[Bool], in: Seq[T]): T =
+    apply(sel zip in)
+  def apply[T <: Data](in: Iterable[(Bool, T)]): T = {
+    if (in.tail.isEmpty) in.head._2
     else {
-      val masked = (sel, in).zipped map ((s, i) => Mux(s, i.toBits, Bits(0)))
-      in.head.fromBits(masked.reduceLeft(_|_))
+      val masked = in map {case (s, i) => Mux(s, i.toBits, Bits(0))}
+      in.head._2.fromBits(masked.reduceLeft(_|_))
     }
   }
-  def apply[T <: Data](in: Iterable[(Bool, T)]): T = {
-    val (sel, data) = in.unzip
-    apply(sel, data)
-  }
-  def apply[T <: Data](sel: Bits, in: Iterable[T]): T =
+  def apply[T <: Data](sel: Bits, in: Seq[T]): T =
     apply((0 until in.size).map(sel(_)), in)
   def apply(sel: Bits, in: Bits): Bool = (sel & in).orR
 }
@@ -107,15 +105,15 @@ object Mux1H
   */
 object PriorityMux
 {
-  def apply[T <: Bits](in: Iterable[(Bool, T)]): T = {
+  def apply[T <: Bits](in: Seq[(Bool, T)]): T = {
     if (in.size == 1) {
       in.head._2
     } else {
       Mux(in.head._1, in.head._2, apply(in.tail))
     }
   }
-  def apply[T <: Bits](sel: Iterable[Bool], in: Iterable[T]): T = apply(sel zip in)
-  def apply[T <: Bits](sel: Bits, in: Iterable[T]): T = apply((0 until in.size).map(sel(_)), in)
+  def apply[T <: Bits](sel: Seq[Bool], in: Seq[T]): T = apply(sel zip in)
+  def apply[T <: Bits](sel: Bits, in: Seq[T]): T = apply((0 until in.size).map(sel(_)), in)
 }
 
 object unless {