5 files changed, 25 insertions, 6 deletions
diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index d65196d9..f299a287 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -10,6 +10,7 @@ package object Chisel {     // scalastyle:ignore package.object.name
   import scala.language.experimental.macros
   import scala.annotation.StaticAnnotation
   import scala.annotation.compileTimeOnly
+  import scala.language.implicitConversions
 
   implicit val defaultCompileOptions = chisel3.core.ExplicitCompileOptions.NotStrict
 
diff --git a/src/test/scala/chiselTests/IOCompatibility.scala b/src/test/scala/chiselTests/IOCompatibility.scala
index 28058963..af64c9f3 100644
--- a/src/test/scala/chiselTests/IOCompatibility.scala
+++ b/src/test/scala/chiselTests/IOCompatibility.scala
@@ -30,7 +30,7 @@ class IOCModuleVec(val n: Int) extends Module {
 
 class IOCModuleWire extends Module {
   val io = IO(new IOCSimpleIO)
-  val inc = Wire(Module(new IOCPlusOne).io.chiselCloneType)
+  val inc = Wire(chiselTypeOf(Module(new IOCPlusOne).io))
   inc.in := io.in
   io.out := inc.out
 }
diff --git a/src/test/scala/chiselTests/InvalidateAPISpec.scala b/src/test/scala/chiselTests/InvalidateAPISpec.scala
index 87a69fe0..c0a643cc 100644
--- a/src/test/scala/chiselTests/InvalidateAPISpec.scala
+++ b/src/test/scala/chiselTests/InvalidateAPISpec.scala
@@ -6,13 +6,15 @@ import chisel3._
 import chisel3.core.BiConnect.BiConnectException
 import chisel3.util.Counter
 import firrtl.passes.CheckInitialization.RefNotInitializedException
+import firrtl.util.BackendCompilationUtilities
 import org.scalatest._
 
-class InvalidateAPISpec extends ChiselPropSpec with Matchers {
+class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompilationUtilities {
 
   def myGenerateFirrtl(t: => Module): String = Driver.emit(() => t)
   def compileFirrtl(t: => Module): Unit = {
-    Driver.execute(Array[String]("--compiler", "verilog"), () => t)
+    val testDir = createTestDirectory(this.getClass.getSimpleName)
+    Driver.execute(Array[String]("-td", testDir.getAbsolutePath, "--compiler", "verilog"), () => t)
   }
   class TrivialInterface extends Bundle {
     val in  = Input(Bool())
diff --git a/src/test/scala/chiselTests/Printf.scala b/src/test/scala/chiselTests/Printf.scala
index 6a0569a2..c1f084c6 100644
--- a/src/test/scala/chiselTests/Printf.scala
+++ b/src/test/scala/chiselTests/Printf.scala
@@ -14,7 +14,7 @@ class SinglePrintfTester() extends BasicTester {
 }
 
 class ASCIIPrintfTester() extends BasicTester {
-  printf((0x20 to 0x7e).map(_ toChar).mkString.replace("%", "%%"))
+  printf((0x20 to 0x7e).map(_.toChar).mkString.replace("%", "%%"))
   stop()
 }
 
diff --git a/src/test/scala/chiselTests/RecordSpec.scala b/src/test/scala/chiselTests/RecordSpec.scala
index d17ff9bd..834153a5 100644
--- a/src/test/scala/chiselTests/RecordSpec.scala
+++ b/src/test/scala/chiselTests/RecordSpec.scala
@@ -5,6 +5,7 @@ package chiselTests
 import chisel3._
 import chisel3.testers.BasicTester
 import chisel3.util.{Counter, Queue}
+import chisel3.experimental.{DataMirror, requireIsChiselType}
 import scala.collection.immutable.ListMap
 
 // An example of how Record might be extended
@@ -12,9 +13,15 @@ import scala.collection.immutable.ListMap
 //   it is a possible implementation of a programmatic "Bundle"
 //   (and can by connected to MyBundle below)
 final class CustomBundle(elts: (String, Data)*) extends Record {
-  val elements = ListMap(elts map { case (field, elt) => field -> elt.chiselCloneType }: _*)
+  val elements = ListMap(elts map { case (field, elt) =>
+    requireIsChiselType(elt)
+    field -> elt
+  }: _*)
   def apply(elt: String): Data = elements(elt)
-  override def cloneType = (new CustomBundle(elements.toList: _*)).asInstanceOf[this.type]
+  override def cloneType = {
+    val cloned = elts.map { case (n, d) => n -> DataMirror.internal.chiselTypeClone(d) }
+    (new CustomBundle(cloned: _*)).asInstanceOf[this.type]
+  }
 }
 
 trait RecordSpecUtils {
@@ -129,4 +136,13 @@ class RecordSpec extends ChiselFlatSpec with RecordSpecUtils {
       elaborate { new MyModule(new CustomBundle("bar" -> UInt(32.W)), fooBarType) }
     }).getMessage should include ("Left Record missing field")
   }
+
+  "CustomBundle" should "work like built-in aggregates" in {
+    elaborate(new Module {
+      val gen = new CustomBundle("foo" -> UInt(32.W))
+      val io = IO(Output(gen))
+      val wire = Wire(gen)
+      io := wire
+    })
+  }
 }