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-rw-r--r--src/main/scala/chisel3/package.scala45
-rw-r--r--src/main/scala/chisel3/util/Decoupled.scala14
-rw-r--r--src/test/scala/chiselTests/Module.scala2
-rw-r--r--src/test/scala/chiselTests/MultiAssign.scala19
-rw-r--r--src/test/scala/chiselTests/Reg.scala18
5 files changed, 51 insertions, 47 deletions
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 35bbd1c4..71ec0e92 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -3,15 +3,21 @@ package object chisel3 {
import internal.firrtl.Width
import internal.sourceinfo.{SourceInfo, SourceInfoTransform}
-
- implicit class fromBigIntToLiteral(val x: BigInt) extends AnyVal {
- def U: UInt = UInt(x, Width())
- def S: SInt = SInt(x, Width())
import util.BitPat
type Direction = chisel3.core.Direction
+ object Input {
+ def apply[T<:Data](target: T): T = chisel3.core.Input(target)
+ }
+ object Output {
+ def apply[T<:Data](target: T): T = chisel3.core.Output(target)
+ }
+ object Flipped {
+ def apply[T<:Data](target: T): T = chisel3.core.Flipped(target)
+ }
+
type Data = chisel3.core.Data
val Wire = chisel3.core.Wire
val Clock = chisel3.core.Clock
@@ -63,30 +69,24 @@ package object chisel3 {
*
* Also provides .asBool to scala.Boolean and .asUInt to String
*
- * Note that, for stylistic reasons, one hould avoid extracting immediately
+ * Note that, for stylistic reasons, one should avoid extracting immediately
* after this call using apply, ie. 0.asUInt(1)(0) due to potential for
* confusion (the 1 is a bit length and the 0 is a bit extraction position).
* Prefer storing the result and then extracting from it.
*/
- implicit class addLiteraltoScalaInt(val target: Int) extends AnyVal {
- def asUInt() = UInt.Lit(target)
- def asSInt() = SInt.Lit(target)
- def asUInt(width: Int) = UInt.Lit(target, width)
- def asSInt(width: Int) = SInt.Lit(target, width)
-
- // These were recently added to chisel2/3 but are not to be used internally
- @deprecated("asUInt should be used over U", "gchisel")
- def U() = UInt.Lit(target)
- @deprecated("asSInt should be used over S", "gchisel")
- def S() = SInt.Lit(target)
- @deprecated("asUInt should be used over U", "gchisel")
- def U(width: Int) = UInt.Lit(target, width)
- @deprecated("asSInt should be used over S", "gchisel")
- def S(width: Int) = SInt.Lit(target, width)
- }
implicit class fromIntToLiteral(val x: Int) extends AnyVal {
def U: UInt = UInt(BigInt(x), Width())
def S: SInt = SInt(BigInt(x), Width())
+
+ def asUInt() = UInt(x, Width())
+ def asSInt() = SInt(x, Width())
+ def asUInt(width: Int) = UInt(x, width)
+ def asSInt(width: Int) = SInt(x, width)
+ }
+
+ implicit class fromBigIntToLiteral(val x: BigInt) extends AnyVal {
+ def U: UInt = UInt(x, Width())
+ def S: SInt = SInt(x, Width())
}
implicit class fromStringToLiteral(val x: String) extends AnyVal {
def U: UInt = UInt(x)
@@ -104,4 +104,7 @@ package object chisel3 {
def do_!= (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that != x
def do_=/= (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that =/= x
}
+
+ val INPUT = chisel3.core.Direction.Input
+ val OUTPUT = chisel3.core.Direction.Output
}
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index 73f58ed4..4a6b72e9 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -12,8 +12,8 @@ class DecoupledIO[+T <: Data](gen: T) extends Bundle
{
val ready = Input(Bool())
val valid = Output(Bool())
- val bits = Output(gen.newType)
- override protected def cloneType: this.type = DecoupledIO(gen).asInstanceOf[this.type]
+ val bits = Output(gen.cloneType)
+ override def cloneType: this.type = DecoupledIO(gen).asInstanceOf[this.type]
}
object DecoupledIO {
@@ -30,7 +30,7 @@ object DecoupledIO {
* @return dat.
*/
def enq(dat: T): T = {
- target.valid := true.asBool
+ target.valid := Bool(true)
target.bits := dat
dat
}
@@ -38,7 +38,7 @@ object DecoupledIO {
/** Indicate no enqueue occurs. Valid is set to false, and all bits are set to zero.
*/
def noenq(): Unit = {
- target.valid := false.asBool
+ target.valid := Bool(false)
target.bits := target.bits.fromBits(0.asUInt)
}
@@ -48,17 +48,17 @@ object DecoupledIO {
* @return the data for this device,
*/
def deq(): T = {
- target.ready := true.asBool
+ target.ready := Bool(true)
target.bits
}
/** Indicate no dequeue occurs. Ready is set to false
*/
def nodeq(): Unit = {
- target.ready := false.asBool
+ target.ready := Bool(false)
}
}
- override def cloneType: this.type = { new DeqIO(gen).asInstanceOf[this.type]; }
+// override def cloneType: this.type = { DeqIO(gen).asInstanceOf[this.type]; }
}
object EnqIO {
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index 7c0bc40e..f1608d5b 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -41,7 +41,7 @@ class ModuleVecTester(c: ModuleVec) extends Tester(c) {
class ModuleWire extends Module {
val io = IO(new SimpleIO)
- val inc = Wire(Module(new PlusOne).io.newType)
+ val inc = Wire(Module(new PlusOne).io.cloneType)
inc.in := io.in
io.out := inc.out
}
diff --git a/src/test/scala/chiselTests/MultiAssign.scala b/src/test/scala/chiselTests/MultiAssign.scala
index d5e9b998..fc6c5edc 100644
--- a/src/test/scala/chiselTests/MultiAssign.scala
+++ b/src/test/scala/chiselTests/MultiAssign.scala
@@ -12,29 +12,30 @@ class LastAssignTester() extends BasicTester {
val cnt = Counter(2)
val test = Wire(UInt(width=4))
- assert(test === UInt.Lit(7)) // allow read references before assign references
+ assert(test === 7.U) // allow read references before assign references
- test := UInt.Lit(13)
- assert(test === UInt.Lit(7)) // output value should be position-independent
+ test := 13.U
+ assert(test === 7.U) // output value should be position-independent
- test := UInt.Lit(7)
- assert(test === UInt.Lit(7)) // this obviously should work
+ test := 7.U
+ assert(test === 7.U) // this obviously should work
- when(cnt.value === UInt.Lit(1)) {
+ when(cnt.value === 1.U) {
stop()
}
}
class ReassignmentTester() extends BasicTester {
- val test = UInt.Lit(15)
- test := UInt.Lit(7)
+ val test = 15.U
+ test := 7.U
}
class MultiAssignSpec extends ChiselFlatSpec {
"The last assignment" should "be used when multiple assignments happen" in {
assertTesterPasses{ new LastAssignTester }
}
- "Reassignments to non-wire types" should "be disallowed" in {
+ intercept[chisel3.internal.ChiselException] {
+// "Reassignments to non-wire types" should "be disallowed" in {
assertTesterFails{ new ReassignmentTester }
}
}
diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala
index 391dd7de..0caf6315 100644
--- a/src/test/scala/chiselTests/Reg.scala
+++ b/src/test/scala/chiselTests/Reg.scala
@@ -16,20 +16,20 @@ class RegSpec extends ChiselFlatSpec {
"A Reg" should "be of the same type and width as outType, if specified" in {
class RegOutTypeWidthTester extends BasicTester {
- val reg = Reg(t=UInt(width=2), next=UInt(width=3), init=UInt(20))
- reg.width.get should be (2)
+ val reg = Reg(t=UInt(width=2), next=Wire(UInt(width=3)), init=UInt(20))
+ reg.getWidth should be (2)
}
elaborate{ new RegOutTypeWidthTester }
}
"A Reg" should "be of unknown width if outType is not specified and width is not forced" in {
class RegUnknownWidthTester extends BasicTester {
- val reg1 = Reg(next=UInt(width=3), init=UInt(20))
- reg1.width.known should be (false)
- val reg2 = Reg(init=UInt(20))
- reg2.width.known should be (false)
- val reg3 = Reg(next=UInt(width=3), init=UInt(width=5))
- reg3.width.known should be (false)
+ val reg1 = Reg(next=Wire(UInt(width=3)), init=20.U)
+ DataMirror.widthOf(reg1).known should be (false)
+ val reg2 = Reg(init=20.U)
+ DataMirror.widthOf(reg2).known should be (false)
+ val reg3 = Reg(next=Wire(UInt(width=3)), init=5.U)
+ DataMirror.widthOf(reg3).known should be (false)
}
elaborate { new RegUnknownWidthTester }
}
@@ -37,7 +37,7 @@ class RegSpec extends ChiselFlatSpec {
"A Reg" should "be of width of init if outType and next are missing and init is a literal of forced width" in {
class RegForcedWidthTester extends BasicTester {
val reg2 = Reg(init=UInt(20, width=7))
- reg2.width.get should be (7)
+ reg2.getWidth should be (7)
}
elaborate{ new RegForcedWidthTester }
}
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-31 21:27:27 +0000