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-rw-r--r--src/main/scala/Chisel/Driver.scala11
-rw-r--r--src/main/scala/Chisel/Main.scala1
2 files changed, 10 insertions, 2 deletions
diff --git a/src/main/scala/Chisel/Driver.scala b/src/main/scala/Chisel/Driver.scala
index a6f61f69..61b74dcd 100644
--- a/src/main/scala/Chisel/Driver.scala
+++ b/src/main/scala/Chisel/Driver.scala
@@ -114,6 +114,13 @@ object Driver extends BackendCompilationUtilities {
f
}
- // FIXME: This is hard coded and should come in from a command-line argument
- def targetDir(): String = { "vsim/generated-src" }
+ private var target_dir: Option[String] = None
+ def parseArgs(args: Array[String]): Unit = {
+ for (i <- 0 until args.size) {
+ if (args(i) == "--targetDir")
+ target_dir = Some(args(i+1))
+ }
+ }
+
+ def targetDir(): String = { target_dir.get }
}
diff --git a/src/main/scala/Chisel/Main.scala b/src/main/scala/Chisel/Main.scala
index 750e8712..349f8b18 100644
--- a/src/main/scala/Chisel/Main.scala
+++ b/src/main/scala/Chisel/Main.scala
@@ -11,6 +11,7 @@ import java.io.File
def run[T <: Module] (args: Array[String], gen: () => T) = {
def circuit = Driver.elaborate(gen)
def output_file = new File(Driver.targetDir + "/" + circuit.name + ".fir")
+ Driver.parseArgs(args)
Driver.dumpFirrtl(circuit, Option(output_file))
}
}