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Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/Chisel/utils.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/Chisel/utils.scala b/src/main/scala/Chisel/utils.scala index e3aff994..f1c5e484 100644 --- a/src/main/scala/Chisel/utils.scala +++ b/src/main/scala/Chisel/utils.scala @@ -530,7 +530,7 @@ object Pipe { def apply[T <: Data](enqValid: Bool, enqBits: T, latency: Int): ValidIO[T] = { if (latency == 0) { - val out = Valid(enqBits) + val out = Wire(Valid(enqBits)) out.valid <> enqValid out.bits <> enqBits out |