2 files changed, 56 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/Mem.scala b/src/test/scala/chiselTests/Mem.scala
index b66ec42f..8bcd3aac 100644
--- a/src/test/scala/chiselTests/Mem.scala
+++ b/src/test/scala/chiselTests/Mem.scala
@@ -96,6 +96,51 @@ class HugeCMemTester(size: BigInt) extends BasicTester {
   }
 }
 
+class SyncReadMemBundleTester extends BasicTester {
+  val (cnt, _) = Counter(true.B, 5)
+  val tpe = new Bundle {
+    val foo = UInt(2.W)
+  }
+  val mem = SyncReadMem(2, tpe)
+  val rdata = mem.read(cnt - 1.U, cnt =/= 0.U)
+
+  switch (cnt) {
+    is (0.U) {
+      val w = Wire(tpe)
+      w.foo := 3.U
+      mem.write(cnt, w)
+    }
+    is (1.U) {
+      val w = Wire(tpe)
+      w.foo := 2.U
+      mem.write(cnt, w)
+    }
+    is (2.U) { assert(rdata.foo === 3.U) }
+    is (3.U) { assert(rdata.foo === 2.U) }
+    is (4.U) { stop() }
+  }
+}
+
+class MemBundleTester extends BasicTester {
+  val tpe = new Bundle {
+    val foo = UInt(2.W)
+  }
+  val mem = Mem(2, tpe)
+
+  // Circuit style tester is definitely the wrong abstraction here
+  val (cnt, wrap) = Counter(true.B, 2)
+  mem(0) := {
+    val w = Wire(tpe)
+    w.foo := 1.U
+    w
+  }
+
+  when (cnt === 1.U) {
+    assert(mem.read(0.U).foo === 1.U)
+    stop()
+  }
+}
+
 class MemorySpec extends ChiselPropSpec {
   property("Mem of Vec should work") {
     assertTesterPasses { new MemVecTester }
@@ -105,6 +150,14 @@ class MemorySpec extends ChiselPropSpec {
     assertTesterPasses { new SyncReadMemTester }
   }
 
+  property("SyncReadMems of Bundles should work") {
+    assertTesterPasses { new SyncReadMemBundleTester }
+  }
+
+  property("Mems of Bundles should work") {
+    assertTesterPasses { new MemBundleTester }
+  }
+
   property("SyncReadMem write collision behaviors should work") {
     assertTesterPasses { new SyncReadMemWriteCollisionTester }
   }
diff --git a/src/test/scala/chiselTests/naming/PrefixSpec.scala b/src/test/scala/chiselTests/naming/PrefixSpec.scala
index 27a9fd39..83408dea 100644
--- a/src/test/scala/chiselTests/naming/PrefixSpec.scala
+++ b/src/test/scala/chiselTests/naming/PrefixSpec.scala
@@ -285,6 +285,7 @@ class PrefixSpec extends ChiselPropSpec with Utils {
         wire.y := RegNext(3.U)
         wire.vec(0) := RegNext(3.U)
         wire.vec(wire.x) := RegNext(3.U)
+        wire.vec(1.U) := RegNext(3.U)
       }
     }
     aspectTest(() => new Test) {
@@ -293,7 +294,8 @@ class PrefixSpec extends ChiselPropSpec with Utils {
           "wire_x_REG",
           "wire_y_REG",
           "wire_vec_0_REG",
-          "wire_vec_REG"
+          "wire_vec_REG",
+          "wire_vec_1_REG"
         ))
     }
   }