diff options
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/chiselTests/ChiselSpec.scala | 2 | ||||
| -rw-r--r-- | src/test/scala/chiselTests/MuxSpec.scala | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/test/scala/chiselTests/ChiselSpec.scala b/src/test/scala/chiselTests/ChiselSpec.scala index 9518fb5c..e50f26e8 100644 --- a/src/test/scala/chiselTests/ChiselSpec.scala +++ b/src/test/scala/chiselTests/ChiselSpec.scala @@ -78,7 +78,7 @@ trait ChiselRunners extends Assertions with BackendCompilationUtilities { .execute(Array("--target-dir", createTestDirectory(this.getClass.getSimpleName).toString), Seq(ChiselGeneratorAnnotation(() => t))) .collectFirst { - case DeletedAnnotation(_, EmittedVerilogCircuitAnnotation(a)) => a.value + case EmittedVerilogCircuitAnnotation(a) => a.value }.getOrElse(fail("No Verilog circuit was emitted by the FIRRTL compiler!")) } } diff --git a/src/test/scala/chiselTests/MuxSpec.scala b/src/test/scala/chiselTests/MuxSpec.scala index a995ea76..71f4cd86 100644 --- a/src/test/scala/chiselTests/MuxSpec.scala +++ b/src/test/scala/chiselTests/MuxSpec.scala @@ -38,7 +38,7 @@ class MuxLookupWrapper(keyWidth: Int, default: Int, mapping: () => Seq[(UInt, UI class MuxLookupExhaustiveSpec extends ChiselPropSpec { val keyWidth = 2 val default = 9 // must be less than 10 to avoid hex/decimal mismatches - val firrtlLit = s"""UInt<4>("h$default")""" + val firrtlLit = s"""UInt<4>("h0$default")""" val stage = new ChiselStage // Assumes there are no literals with 'UInt<4>("h09")' in the output FIRRTL |