diff options
Diffstat (limited to 'src/test')
31 files changed, 554 insertions, 240 deletions
diff --git a/src/test/scala/chiselTests/Assert.scala b/src/test/scala/chiselTests/Assert.scala index 3fed2bd4..efc2e1e7 100644 --- a/src/test/scala/chiselTests/Assert.scala +++ b/src/test/scala/chiselTests/Assert.scala @@ -26,7 +26,7 @@ class SucceedingAssertTester() extends BasicTester { } class PipelinedResetModule extends Module { - val io = new Bundle { } + val io = IO(new Bundle { }) val a = Reg(init = UInt(0xbeef)) val b = Reg(init = UInt(0xbeef)) assert(a === b) diff --git a/src/test/scala/chiselTests/BetterNamingTests.scala b/src/test/scala/chiselTests/BetterNamingTests.scala index 44fc542a..f5872adb 100644 --- a/src/test/scala/chiselTests/BetterNamingTests.scala +++ b/src/test/scala/chiselTests/BetterNamingTests.scala @@ -3,8 +3,8 @@ package chiselTests import org.scalatest.{FlatSpec, Matchers} import collection.mutable -import Chisel._ - +import chisel3._ +import chisel3.util._ // Defined outside of the class so we don't get $ in name class Other(w: Int) extends Module { diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala index fdc5970e..344754e1 100644 --- a/src/test/scala/chiselTests/BlackBox.scala +++ b/src/test/scala/chiselTests/BlackBox.scala @@ -8,27 +8,28 @@ import org.scalatest._ import chisel3._ import chisel3.testers.BasicTester import chisel3.util._ +//import chisel3.core.ExplicitCompileOptions.Strict class BlackBoxInverter extends BlackBox { - val io = new Bundle() { - val in = Bool(INPUT) - val out = Bool(OUTPUT) - } + val io = IO(new Bundle() { + val in = Input(Bool()) + val out = Output(Bool()) + }) } class BlackBoxPassthrough extends BlackBox { - val io = new Bundle() { - val in = Bool(INPUT) - val out = Bool(OUTPUT) - } + val io = IO(new Bundle() { + val in = Input(Bool()) + val out = Output(Bool()) + }) } class BlackBoxRegister extends BlackBox { - val io = new Bundle() { - val clock = Clock().asInput - val in = Bool(INPUT) - val out = Bool(OUTPUT) - } + val io = IO(new Bundle() { + val clock = Input(Clock()) + val in = Input(Bool()) + val out = Output(Bool()) + }) } class BlackBoxTester extends BasicTester { @@ -86,9 +87,9 @@ class BlackBoxWithClockTester extends BasicTester { /* // Must determine how to handle parameterized Verilog class BlackBoxConstant(value: Int) extends BlackBox { - val io = new Bundle() { - val out = UInt(width=log2Up(value)).asOutput - } + val io = IO(new Bundle() { + val out = Output(UInt(width=log2Up(value))) + }) override val name = s"#(WIDTH=${log2Up(value)},VALUE=$value) " } diff --git a/src/test/scala/chiselTests/BundleWire.scala b/src/test/scala/chiselTests/BundleWire.scala index e5e9fb1a..53d46e93 100644 --- a/src/test/scala/chiselTests/BundleWire.scala +++ b/src/test/scala/chiselTests/BundleWire.scala @@ -5,17 +5,18 @@ import chisel3._ import org.scalatest._ import org.scalatest.prop._ import chisel3.testers.BasicTester +//import chisel3.core.ExplicitCompileOptions.Strict class Coord extends Bundle { - val x = UInt(width = 32) - val y = UInt(width = 32) + val x = UInt.width( 32) + val y = UInt.width( 32) } class BundleWire(n: Int) extends Module { - val io = new Bundle { - val in = (new Coord).asInput - val outs = Vec(n, new Coord).asOutput - } + val io = IO(new Bundle { + val in = Input(new Coord) + val outs = Output(Vec(n, new Coord)) + }) val coords = Wire(Vec(n, new Coord)) for (i <- 0 until n) { coords(i) := io.in diff --git a/src/test/scala/chiselTests/CompileOptionsTest.scala b/src/test/scala/chiselTests/CompileOptionsTest.scala new file mode 100644 index 00000000..83077544 --- /dev/null +++ b/src/test/scala/chiselTests/CompileOptionsTest.scala @@ -0,0 +1,281 @@ +// See LICENSE for license details. + +package chiselTests + +import org.scalatest._ +import chisel3._ +import chisel3.core.Binding.BindingException +import chisel3.core.ExplicitCompileOptions +import chisel3.testers.BasicTester +import chisel3.core.CompileOptions + +class CompileOptionsSpec extends ChiselFlatSpec { + + abstract class StrictModule extends Module()(chisel3.core.ExplicitCompileOptions.Strict) + abstract class NotStrictModule extends Module()(chisel3.core.ExplicitCompileOptions.NotStrict) + + // Generate a set of options that do not have requireIOWrap enabled, in order to + // ensure its definition comes from the implicit options passed to the Module constructor. + object StrictWithoutIOWrap extends CompileOptions { + val connectFieldsMustMatch = true + val declaredTypeMustBeUnbound = true + val requireIOWrap = false + val dontTryConnectionsSwapped = true + val dontAssumeDirectionality = true + } + + class SmallBundle extends Bundle { + val f1 = UInt(width = 4) + val f2 = UInt(width = 5) + override def cloneType: this.type = (new SmallBundle).asInstanceOf[this.type] + } + class BigBundle extends SmallBundle { + val f3 = UInt(width = 6) + override def cloneType: this.type = (new BigBundle).asInstanceOf[this.type] + } + + "A Module with missing bundle fields when compiled with implicit Strict.CompileOption " should "throw an exception" in { + a [ChiselException] should be thrownBy { + import chisel3.core.ExplicitCompileOptions.Strict + + class ConnectFieldMismatchModule extends Module { + val io = IO(new Bundle { + val in = Input(new SmallBundle) + val out = Output(new BigBundle) + }) + io.out := io.in + } + elaborate { new ConnectFieldMismatchModule() } + } + } + + "A Module with missing bundle fields when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in { + import chisel3.core.ExplicitCompileOptions.NotStrict + + class ConnectFieldMismatchModule extends Module { + val io = IO(new Bundle { + val in = Input(new SmallBundle) + val out = Output(new BigBundle) + }) + io.out := io.in + } + elaborate { new ConnectFieldMismatchModule() } + } + + "A Module in which a Reg is created with a bound type when compiled with implicit Strict.CompileOption " should "throw an exception" in { + a [BindingException] should be thrownBy { + import chisel3.core.ExplicitCompileOptions.Strict + + class CreateRegFromBoundTypeModule extends Module { + val io = IO(new Bundle { + val in = Input(new SmallBundle) + val out = Output(new BigBundle) + }) + val badReg = Reg(UInt(7, width=4)) + } + elaborate { new CreateRegFromBoundTypeModule() } + } + } + + "A Module in which a Reg is created with a bound type when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in { + import chisel3.core.ExplicitCompileOptions.NotStrict + + class CreateRegFromBoundTypeModule extends Module { + val io = IO(new Bundle { + val in = Input(new SmallBundle) + val out = Output(new BigBundle) + }) + val badReg = Reg(UInt(7, width=4)) + } + elaborate { new CreateRegFromBoundTypeModule() } + } + + "A Module with wrapped IO when compiled with implicit Strict.CompileOption " should "not throw an exception" in { + import chisel3.core.ExplicitCompileOptions.Strict + + class RequireIOWrapModule extends Module { + val io = IO(new Bundle { + val in = UInt(width = 32).asInput + val out = Bool().asOutput + }) + io.out := io.in(1) + } + elaborate { new RequireIOWrapModule() } +} + + "A Module with unwrapped IO when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in { + import chisel3.core.ExplicitCompileOptions.NotStrict + + class RequireIOWrapModule extends Module { + val io = new Bundle { + val in = UInt(width = 32).asInput + val out = Bool().asOutput + } + io.out := io.in(1) + } + elaborate { new RequireIOWrapModule() } + } + + "A Module with unwrapped IO when compiled with implicit Strict.CompileOption " should "throw an exception" in { + a [BindingException] should be thrownBy { + import chisel3.core.ExplicitCompileOptions.Strict + + class RequireIOWrapModule extends Module { + val io = new Bundle { + val in = UInt(width = 32).asInput + val out = Bool().asOutput + } + io.out := io.in(1) + } + elaborate { + new RequireIOWrapModule() + } + } + } + + "A Module connecting output as source to input as sink when compiled with implicit Strict.CompileOption " should "throw an exception" in { + a [ChiselException] should be thrownBy { + import chisel3.core.ExplicitCompileOptions.Strict + + class SimpleModule extends Module { + val io = IO(new Bundle { + val in = Input(UInt(width = 3)) + val out = Output(UInt(width = 4)) + }) + } + class SwappedConnectionModule extends SimpleModule { + val child = Module(new SimpleModule) + io.in := child.io.out + } + elaborate { new SwappedConnectionModule() } + } + } + + "A Module connecting output as source to input as sink when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in { + import chisel3.core.ExplicitCompileOptions.NotStrict + + class SimpleModule extends Module { + val io = IO(new Bundle { + val in = Input(UInt(width = 3)) + val out = Output(UInt(width = 4)) + }) + } + class SwappedConnectionModule extends SimpleModule { + val child = Module(new SimpleModule) + io.in := child.io.out + } + elaborate { new SwappedConnectionModule() } + } + + "A Module with directionless connections when compiled with implicit Strict.CompileOption " should "throw an exception" in { + a [ChiselException] should be thrownBy { + // Verify we can suppress the inclusion of default compileOptions + import Chisel.{defaultCompileOptions => _, _} + import chisel3.core.ExplicitCompileOptions.Strict + + class SimpleModule extends Module { + val io = IO(new Bundle { + val in = Input(UInt(width = 3)) + val out = Output(UInt(width = 4)) + }) + val noDir = Wire(UInt(width = 3)) + } + + class DirectionLessConnectionModule extends SimpleModule { + val a = UInt(0, width = 3) + val b = Wire(UInt(width = 3)) + val child = Module(new SimpleModule) + b := child.noDir + } + elaborate { new DirectionLessConnectionModule() } + } + } + + "A Module with directionless connections when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in { + import chisel3.core.ExplicitCompileOptions.NotStrict + + class SimpleModule extends Module { + val io = IO(new Bundle { + val in = Input(UInt(width = 3)) + val out = Output(UInt(width = 4)) + }) + val noDir = Wire(UInt(width = 3)) + } + + class DirectionLessConnectionModule extends SimpleModule { + val a = UInt(0, width = 3) + val b = Wire(UInt(width = 3)) + val child = Module(new SimpleModule) + b := child.noDir + } + elaborate { new DirectionLessConnectionModule() } + } + + "A Module with wrapped IO when compiled with explicit Strict.CompileOption " should "not throw an exception" in { + implicit val strictWithoutIOWrap = StrictWithoutIOWrap + class RequireIOWrapModule extends StrictModule { + val io = IO(new Bundle { + val in = UInt(width = 32).asInput + val out = Bool().asOutput + }) + io.out := io.in(1) + } + elaborate { + new RequireIOWrapModule() + } + } + + "A Module with unwrapped IO when compiled with explicit NotStrict.CompileOption " should "not throw an exception" in { + implicit val strictWithoutIOWrap = StrictWithoutIOWrap + class RequireIOWrapModule extends NotStrictModule { + val io = new Bundle { + val in = UInt(width = 32).asInput + val out = Bool().asOutput + } + io.out := io.in(1) + } + elaborate { + new RequireIOWrapModule() + } + } + + "A Module with unwrapped IO when compiled with explicit Strict.CompileOption " should "throw an exception" in { + a [BindingException] should be thrownBy { + implicit val strictWithoutIOWrap = StrictWithoutIOWrap + class RequireIOWrapModule extends StrictModule { + val io = new Bundle { + val in = UInt(width = 32).asInput + val out = Bool().asOutput + } + io.out := io.in(1) + } + elaborate { + new RequireIOWrapModule() + } + } + } + + "A Module with unwrapped IO when compiled with an explicit requireIOWrap false " should "not throw an exception" in { + + object StrictNotIOWrap { + + implicit object CompileOptions extends CompileOptions { + val connectFieldsMustMatch = true + val declaredTypeMustBeUnbound = true + val requireIOWrap = false + val dontTryConnectionsSwapped = true + val dontAssumeDirectionality = true + } + + } + class NotIOWrapModule extends Module()(StrictNotIOWrap.CompileOptions) { + val io = new Bundle { + val in = UInt(width = 32).asInput + val out = Bool().asOutput + } + } + elaborate { + new NotIOWrapModule() + } + } +} diff --git a/src/test/scala/chiselTests/ComplexAssign.scala b/src/test/scala/chiselTests/ComplexAssign.scala index 304fbcf5..0a1f31cc 100644 --- a/src/test/scala/chiselTests/ComplexAssign.scala +++ b/src/test/scala/chiselTests/ComplexAssign.scala @@ -11,17 +11,17 @@ import chisel3.util._ class Complex[T <: Data](val re: T, val im: T) extends Bundle { override def cloneType: this.type = - new Complex(re.cloneType, im.cloneType).asInstanceOf[this.type] + new Complex(re.chiselCloneType, im.chiselCloneType).asInstanceOf[this.type] } class ComplexAssign(w: Int) extends Module { - val io = new Bundle { - val e = new Bool(INPUT) - val in = new Complex(UInt(width = w), UInt(width = w)).asInput - val out = new Complex(UInt(width = w), UInt(width = w)).asOutput - } + val io = IO(new Bundle { + val e = Input(Bool()) + val in = Input(new Complex(UInt.width(w), UInt.width(w))) + val out = Output(new Complex(UInt.width(w), UInt.width(w))) + }) when (io.e) { - val tmp = Wire(new Complex(UInt(width = w), UInt(width = w))) + val tmp = Wire(new Complex(UInt.width(w), UInt.width(w))) tmp := io.in io.out.re := tmp.re io.out.im := tmp.im diff --git a/src/test/scala/chiselTests/Decoder.scala b/src/test/scala/chiselTests/Decoder.scala index 5586561b..b50a80c0 100644 --- a/src/test/scala/chiselTests/Decoder.scala +++ b/src/test/scala/chiselTests/Decoder.scala @@ -11,10 +11,10 @@ import chisel3.testers.BasicTester import chisel3.util._ class Decoder(bitpats: List[String]) extends Module { - val io = new Bundle { - val inst = UInt(INPUT, 32) - val matched = Bool(OUTPUT) - } + val io = IO(new Bundle { + val inst = Input(UInt.width(32)) + val matched = Output(Bool()) + }) io.matched := Vec(bitpats.map(BitPat(_) === io.inst)).reduce(_||_) } diff --git a/src/test/scala/chiselTests/DeqIOSpec.scala b/src/test/scala/chiselTests/DeqIOSpec.scala index 09891647..d41c50e5 100644 --- a/src/test/scala/chiselTests/DeqIOSpec.scala +++ b/src/test/scala/chiselTests/DeqIOSpec.scala @@ -12,21 +12,21 @@ import chisel3.util._ class UsesDeqIOInfo extends Bundle { val test_width = 32 - val info_data = UInt(width = test_width) + val info_data = UInt.width(test_width) } class UsesDeqIO extends Module { - val io = new Bundle { - val in = new DeqIO(new UsesDeqIOInfo) - val out = new EnqIO(new UsesDeqIOInfo) - } + val io = IO(new Bundle { + val in = chisel3.util.DeqIO(new UsesDeqIOInfo) + val out = chisel3.util.EnqIO(new UsesDeqIOInfo) + }) } class DeqIOSpec extends ChiselFlatSpec { runTester { new BasicTester { val dut = new UsesDeqIO - +/* "DeqIO" should "set the direction of it's parameter to INPUT" in { assert(dut.io.in.bits.info_data.dir === INPUT) } @@ -56,6 +56,7 @@ class DeqIOSpec extends ChiselFlatSpec { assert(dut.io.out.ready.dir == out_clone.ready.dir) assert(dut.io.out.valid.dir == out_clone.valid.dir) } + */ } } } diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala index 8b84f844..949b92ed 100644 --- a/src/test/scala/chiselTests/Direction.scala +++ b/src/test/scala/chiselTests/Direction.scala @@ -8,10 +8,10 @@ import org.scalatest.prop._ import chisel3.testers.BasicTester class DirectionHaver extends Module { - val io = new Bundle { - val in = UInt(INPUT, 32) - val out = UInt(OUTPUT, 32) - } + val io = IO(new Bundle { + val in = Input(UInt.width(32)) + val out = Output(UInt.width(32)) + }) } class GoodDirection extends DirectionHaver { @@ -22,7 +22,7 @@ class BadDirection extends DirectionHaver { io.in := UInt(0) } -class DirectionSpec extends ChiselPropSpec { +class DirectionSpec extends ChiselPropSpec with ShouldMatchers { //TODO: In Chisel3 these are actually FIRRTL errors. Remove from tests? @@ -31,7 +31,8 @@ class DirectionSpec extends ChiselPropSpec { } property("Inputs should not be assignable") { - elaborate(new BadDirection) + a[Exception] should be thrownBy { + elaborate(new BadDirection) + } } - } diff --git a/src/test/scala/chiselTests/EnableShiftRegister.scala b/src/test/scala/chiselTests/EnableShiftRegister.scala index 7db20fc1..5f3e0dd1 100644 --- a/src/test/scala/chiselTests/EnableShiftRegister.scala +++ b/src/test/scala/chiselTests/EnableShiftRegister.scala @@ -5,11 +5,11 @@ import chisel3._ import chisel3.testers.BasicTester class EnableShiftRegister extends Module { - val io = new Bundle { - val in = UInt(INPUT, 4) - val shift = Bool(INPUT) - val out = UInt(OUTPUT, 4) - } + val io = IO(new Bundle { + val in = Input(UInt.width(4)) + val shift = Input(Bool()) + val out = Output(UInt.width(4)) + }) val r0 = Reg(init = UInt(0, 4)) val r1 = Reg(init = UInt(0, 4)) val r2 = Reg(init = UInt(0, 4)) diff --git a/src/test/scala/chiselTests/GCD.scala b/src/test/scala/chiselTests/GCD.scala index 23df3256..d683ce34 100644 --- a/src/test/scala/chiselTests/GCD.scala +++ b/src/test/scala/chiselTests/GCD.scala @@ -8,31 +8,31 @@ import org.scalatest._ import org.scalatest.prop._ class GCD extends Module { - val io = new Bundle { - val a = UInt(INPUT, 32) - val b = UInt(INPUT, 32) - val e = Bool(INPUT) - val z = UInt(OUTPUT, 32) - val v = Bool(OUTPUT) - } - val x = Reg(UInt(width = 32)) - val y = Reg(UInt(width = 32)) + val io = IO(new Bundle { + val a = Input(UInt.width(32)) + val b = Input(UInt.width(32)) + val e = Input(Bool()) + val z = Output(UInt.width(32)) + val v = Output(Bool()) + }) + val x = Reg(UInt.width( 32)) + val y = Reg(UInt.width( 32)) when (x > y) { x := x -% y } .otherwise { y := y -% x } when (io.e) { x := io.a; y := io.b } io.z := x - io.v := y === UInt(0) + io.v := y === 0.U } class GCDTester(a: Int, b: Int, z: Int) extends BasicTester { val dut = Module(new GCD) - val first = Reg(init=Bool(true)) - dut.io.a := UInt(a) - dut.io.b := UInt(b) + val first = Reg(init=true.B) + dut.io.a := a.U + dut.io.b := b.U dut.io.e := first when(first) { first := Bool(false) } when(!first && dut.io.v) { - assert(dut.io.z === UInt(z)) + assert(dut.io.z === z.U) stop() } } diff --git a/src/test/scala/chiselTests/IOCompatibility.scala b/src/test/scala/chiselTests/IOCompatibility.scala new file mode 100644 index 00000000..7bf3dded --- /dev/null +++ b/src/test/scala/chiselTests/IOCompatibility.scala @@ -0,0 +1,45 @@ +// See LICENSE for license details. + +package chiselTests + +import chisel3._ + +class IOCSimpleIO extends Bundle { + val in = Input(UInt(width=32)) + val out = Output(UInt(width=32)) +} + +class IOCPlusOne extends Module { + val io = IO(new IOCSimpleIO) + io.out := io.in + UInt(1) +} + +class IOCModuleVec(val n: Int) extends Module { + val io = IO(new Bundle { + val ins = Vec(n, Input(UInt(width=32))) + val outs = Vec(n, Output(UInt(width=32))) + }) + val pluses = Vec.fill(n){ Module(new IOCPlusOne).io } + for (i <- 0 until n) { + pluses(i).in := io.ins(i) + io.outs(i) := pluses(i).out + } +} + +class IOCModuleWire extends Module { + val io = IO(new IOCSimpleIO) + val inc = Wire(Module(new IOCPlusOne).io.chiselCloneType) + inc.in := io.in + io.out := inc.out +} + +class IOCompatibilitySpec extends ChiselPropSpec { + + property("IOCModuleVec should elaborate") { + elaborate { new IOCModuleVec(2) } + } + + property("IOCModuleWire should elaborate") { + elaborate { new IOCModuleWire } + } +} diff --git a/src/test/scala/chiselTests/LFSR16.scala b/src/test/scala/chiselTests/LFSR16.scala index a1699441..b13b67e3 100644 --- a/src/test/scala/chiselTests/LFSR16.scala +++ b/src/test/scala/chiselTests/LFSR16.scala @@ -7,10 +7,10 @@ import chisel3.testers.BasicTester import chisel3.util._ class LFSR16 extends Module { - val io = new Bundle { - val inc = Bool(INPUT) - val out = UInt(OUTPUT, 16) - } + val io = IO(new Bundle { + val inc = Input(Bool()) + val out = Output(UInt.width(16)) + }) val res = Reg(init = UInt(1, 16)) when (io.inc) { val nxt_res = Cat(res(0)^res(2)^res(3)^res(5), res(15,1)) diff --git a/src/test/scala/chiselTests/MemorySearch.scala b/src/test/scala/chiselTests/MemorySearch.scala index 679b894c..1d09f3c5 100644 --- a/src/test/scala/chiselTests/MemorySearch.scala +++ b/src/test/scala/chiselTests/MemorySearch.scala @@ -6,12 +6,12 @@ import chisel3._ import chisel3.testers.BasicTester class MemorySearch extends Module { - val io = new Bundle { - val target = UInt(INPUT, 4) - val en = Bool(INPUT) - val done = Bool(OUTPUT) - val address = UInt(OUTPUT, 3) - } + val io = IO(new Bundle { + val target = Input(UInt.width(4)) + val en = Input(Bool()) + val done = Output(Bool()) + val address = Output(UInt.width(3)) + }) val vals = Array(0, 4, 15, 14, 2, 5, 13) val index = Reg(init = UInt(0, width = 3)) val elts = Vec(vals.map(UInt(_,4))) diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala index 23788b72..7a4050db 100644 --- a/src/test/scala/chiselTests/Module.scala +++ b/src/test/scala/chiselTests/Module.scala @@ -5,20 +5,20 @@ package chiselTests import chisel3._ class SimpleIO extends Bundle { - val in = UInt(INPUT, 32) - val out = UInt(OUTPUT, 32) + val in = Input(UInt.width(32)) + val out = Output(UInt.width(32)) } class PlusOne extends Module { - val io = new SimpleIO - io.out := io.in + UInt(1) + val io = IO(new SimpleIO) + io.out := io.in + 1.asUInt } class ModuleVec(val n: Int) extends Module { - val io = new Bundle { - val ins = Vec(n, UInt(INPUT, 32)) - val outs = Vec(n, UInt(OUTPUT, 32)) - } + val io = IO(new Bundle { + val ins = Input(Vec(n, UInt(32))) + val outs = Output(Vec(n, UInt(32))) + }) val pluses = Vec.fill(n){ Module(new PlusOne).io } for (i <- 0 until n) { pluses(i).in := io.ins(i) @@ -40,8 +40,8 @@ class ModuleVecTester(c: ModuleVec) extends Tester(c) { */ class ModuleWire extends Module { - val io = new SimpleIO - val inc = Wire(Module(new PlusOne).io) + val io = IO(new SimpleIO) + val inc = Wire(Module(new PlusOne).io.chiselCloneType) inc.in := io.in io.out := inc.out } @@ -58,10 +58,10 @@ class ModuleWireTester(c: ModuleWire) extends Tester(c) { */ class ModuleWhen extends Module { - val io = new Bundle { + val io = IO(new Bundle { val s = new SimpleIO val en = Bool() - } + }) when(io.en) { val inc = Module(new PlusOne).io inc.in := io.s.in diff --git a/src/test/scala/chiselTests/MulLookup.scala b/src/test/scala/chiselTests/MulLookup.scala index 831e323f..26ee4e03 100644 --- a/src/test/scala/chiselTests/MulLookup.scala +++ b/src/test/scala/chiselTests/MulLookup.scala @@ -8,11 +8,11 @@ import org.scalatest.prop._ import chisel3.testers.BasicTester class MulLookup(val w: Int) extends Module { - val io = new Bundle { - val x = UInt(INPUT, w) - val y = UInt(INPUT, w) - val z = UInt(OUTPUT, 2 * w) - } + val io = IO(new Bundle { + val x = Input(UInt.width(w)) + val y = Input(UInt.width(w)) + val z = Output(UInt.width(2 * w)) + }) val tbl = Vec( for { i <- 0 until 1 << w diff --git a/src/test/scala/chiselTests/MultiAssign.scala b/src/test/scala/chiselTests/MultiAssign.scala index c22a5e30..fa4c4898 100644 --- a/src/test/scala/chiselTests/MultiAssign.scala +++ b/src/test/scala/chiselTests/MultiAssign.scala @@ -11,30 +11,35 @@ import chisel3.util._ class LastAssignTester() extends BasicTester { val cnt = Counter(2) - val test = Wire(UInt(width=4)) - assert(test === UInt(7)) // allow read references before assign references + val test = Wire(UInt.width(4)) + assert(test === 7.U) // allow read references before assign references - test := UInt(13) - assert(test === UInt(7)) // output value should be position-independent + test := 13.U + assert(test === 7.U) // output value should be position-independent - test := UInt(7) - assert(test === UInt(7)) // this obviously should work + test := 7.U + assert(test === 7.U) // this obviously should work - when(cnt.value === UInt(1)) { + when(cnt.value === 1.U) { stop() } } class ReassignmentTester() extends BasicTester { - val test = UInt(15) - test := UInt(7) + val test = 15.U + test := 7.U } class MultiAssignSpec extends ChiselFlatSpec { "The last assignment" should "be used when multiple assignments happen" in { assertTesterPasses{ new LastAssignTester } } +} + +class IllegalAssignSpec extends ChiselFlatSpec { "Reassignments to non-wire types" should "be disallowed" in { - assertTesterFails{ new ReassignmentTester } + intercept[chisel3.internal.ChiselException] { + assertTesterFails{ new ReassignmentTester } + } } } diff --git a/src/test/scala/chiselTests/OptionBundle.scala b/src/test/scala/chiselTests/OptionBundle.scala index fa691b43..8e4c7579 100644 --- a/src/test/scala/chiselTests/OptionBundle.scala +++ b/src/test/scala/chiselTests/OptionBundle.scala @@ -8,15 +8,15 @@ import chisel3.testers.BasicTester class OptionBundle(hasIn: Boolean) extends Bundle { val in = if (hasIn) { - Some(Bool(INPUT)) + Some(Input(Bool())) } else { None } - val out = Bool(OUTPUT) + val out = Output(Bool()) } class OptionBundleModule(hasIn: Boolean) extends Module { - val io = new OptionBundle(hasIn) + val io = IO(new OptionBundle(hasIn)) if (hasIn) { io.out := io.in.get } else { diff --git a/src/test/scala/chiselTests/Padding.scala b/src/test/scala/chiselTests/Padding.scala index 3fb0f955..42df6802 100644 --- a/src/test/scala/chiselTests/Padding.scala +++ b/src/test/scala/chiselTests/Padding.scala @@ -5,11 +5,11 @@ package chiselTests import chisel3._ class Padder extends Module { - val io = new Bundle { - val a = Bits(INPUT, 4) - val asp = SInt(OUTPUT, 8) - val aup = UInt(OUTPUT, 8) - } + val io = IO(new Bundle { + val a = Input(UInt.width(4)) + val asp = Output(SInt.width(8)) + val aup = Output(UInt.width(8)) + }) io.asp := io.a.asSInt io.aup := io.a.asUInt } diff --git a/src/test/scala/chiselTests/ParameterizedModule.scala b/src/test/scala/chiselTests/ParameterizedModule.scala index 4859759e..14b21631 100644 --- a/src/test/scala/chiselTests/ParameterizedModule.scala +++ b/src/test/scala/chiselTests/ParameterizedModule.scala @@ -7,10 +7,10 @@ import chisel3._ import chisel3.testers.BasicTester class ParameterizedModule(invert: Boolean) extends Module { - val io = new Bundle { - val in = new Bool(INPUT) - val out = new Bool(OUTPUT) - } + val io = IO(new Bundle { + val in = Input(Bool()) + val out = Output(Bool()) + }) if (invert) { io.out := !io.in } else { diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala index a92d5ebf..a9086223 100644 --- a/src/test/scala/chiselTests/Reg.scala +++ b/src/test/scala/chiselTests/Reg.scala @@ -4,6 +4,7 @@ package chiselTests import org.scalatest._ import chisel3._ +import chisel3.core.DataMirror import chisel3.testers.BasicTester class RegSpec extends ChiselFlatSpec { @@ -15,7 +16,7 @@ class RegSpec extends ChiselFlatSpec { "A Reg" should "be of the same type and width as outType, if specified" in { class RegOutTypeWidthTester extends BasicTester { - val reg = Reg(t=UInt(width=2), next=UInt(width=3), init=UInt(20)) + val reg = Reg(t=UInt(width=2), next=Wire(UInt(width=3)), init=UInt(20)) reg.getWidth should be (2) } elaborate{ new RegOutTypeWidthTester } @@ -23,12 +24,15 @@ class RegSpec extends ChiselFlatSpec { "A Reg" should "be of unknown width if outType is not specified and width is not forced" in { class RegUnknownWidthTester extends BasicTester { - val reg1 = Reg(next=UInt(width=3), init=UInt(20)) + val reg1 = Reg(next=Wire(UInt(width=3)), init=UInt(20)) reg1.isWidthKnown should be (false) + DataMirror.widthOf(reg1).known should be (false) val reg2 = Reg(init=UInt(20)) reg2.isWidthKnown should be (false) - val reg3 = Reg(next=UInt(width=3), init=UInt(width=5)) + DataMirror.widthOf(reg2).known should be (false) + val reg3 = Reg(next=Wire(UInt(width=3)), init=UInt(5)) reg3.isWidthKnown should be (false) + DataMirror.widthOf(reg3).known should be (false) } elaborate { new RegUnknownWidthTester } } diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala index f5e61115..6d5a0a76 100644 --- a/src/test/scala/chiselTests/Risc.scala +++ b/src/test/scala/chiselTests/Risc.scala @@ -6,20 +6,20 @@ import chisel3._ import chisel3.util._ class Risc extends Module { - val io = new Bundle { - val isWr = Bool(INPUT) - val wrAddr = UInt(INPUT, 8) - val wrData = Bits(INPUT, 32) - val boot = Bool(INPUT) - val valid = Bool(OUTPUT) - val out = Bits(OUTPUT, 32) - } + val io = IO(new Bundle { + val isWr = Input(Bool()) + val wrAddr = Input(UInt.width(8)) + val wrData = Input(Bits.width(32)) + val boot = Input(Bool()) + val valid = Output(Bool()) + val out = Output(Bits.width(32)) + }) val memSize = 256 - val file = Mem(memSize, Bits(width = 32)) - val code = Mem(memSize, Bits(width = 32)) + val file = Mem(memSize, Bits.width(32)) + val code = Mem(memSize, Bits.width(32)) val pc = Reg(init=UInt(0, 8)) - val add_op :: imm_op :: Nil = Enum(Bits(width = 8), 2) + val add_op :: imm_op :: Nil = Enum(Bits.width(8), 2) val inst = code(pc) val op = inst(31,24) @@ -27,13 +27,13 @@ class Risc extends Module { val rai = inst(15, 8) val rbi = inst( 7, 0) - val ra = Mux(rai === Bits(0), Bits(0), file(rai)) - val rb = Mux(rbi === Bits(0), Bits(0), file(rbi)) - val rc = Wire(Bits(width = 32)) + val ra = Mux(rai === 0.asUInt(), 0.asUInt(), file(rai)) + val rb = Mux(rbi === 0.asUInt(), 0.asUInt(), file(rbi)) + val rc = Wire(Bits.width(32)) io.valid := Bool(false) - io.out := Bits(0) - rc := Bits(0) + io.out := 0.asUInt() + rc := 0.asUInt() when (io.isWr) { code(io.wrAddr) := io.wrData @@ -45,12 +45,12 @@ class Risc extends Module { is(imm_op) { rc := (rai << 8) | rbi } } io.out := rc - when (rci === UInt(255)) { + when (rci === 255.asUInt()) { io.valid := Bool(true) } .otherwise { file(rci) := rc } - pc := pc +% UInt(1) + pc := pc +% 1.asUInt() } } diff --git a/src/test/scala/chiselTests/SIntOps.scala b/src/test/scala/chiselTests/SIntOps.scala index 6cd013f1..392c4803 100644 --- a/src/test/scala/chiselTests/SIntOps.scala +++ b/src/test/scala/chiselTests/SIntOps.scala @@ -6,24 +6,24 @@ import chisel3._ import chisel3.testers.BasicTester class SIntOps extends Module { - val io = new Bundle { - val a = SInt(INPUT, 16) - val b = SInt(INPUT, 16) - val addout = SInt(OUTPUT, 16) - val subout = SInt(OUTPUT, 16) - val timesout = SInt(OUTPUT, 16) - val divout = SInt(OUTPUT, 16) - val modout = SInt(OUTPUT, 16) - val lshiftout = SInt(OUTPUT, 16) - val rshiftout = SInt(OUTPUT, 16) - val lessout = Bool(OUTPUT) - val greatout = Bool(OUTPUT) - val eqout = Bool(OUTPUT) - val noteqout = Bool(OUTPUT) - val lesseqout = Bool(OUTPUT) - val greateqout = Bool(OUTPUT) - val negout = SInt(OUTPUT, 16) - } + val io = IO(new Bundle { + val a = Input(SInt.width(16)) + val b = Input(SInt.width(16)) + val addout = Output(SInt.width(16)) + val subout = Output(SInt.width(16)) + val timesout = Output(SInt.width(16)) + val divout = Output(SInt.width(16)) + val modout = Output(SInt.width(16)) + val lshiftout = Output(SInt.width(16)) + val rshiftout = Output(SInt.width(16)) + val lessout = Output(Bool()) + val greatout = Output(Bool()) + val eqout = Output(Bool()) + val noteqout = Output(Bool()) + val lesseqout = Output(Bool()) + val greateqout = Output(Bool()) + val negout = Output(SInt.width(16)) + }) val a = io.a val b = io.b diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala index cbd9f3e3..a72af928 100644 --- a/src/test/scala/chiselTests/Stack.scala +++ b/src/test/scala/chiselTests/Stack.scala @@ -8,15 +8,15 @@ import chisel3._ import chisel3.util._ class ChiselStack(val depth: Int) extends Module { - val io = new Bundle { - val push = Bool(INPUT) - val pop = Bool(INPUT) - val en = Bool(INPUT) - val dataIn = UInt(INPUT, 32) - val dataOut = UInt(OUTPUT, 32) - } + val io = IO(new Bundle { + val push = Input(Bool()) + val pop = Input(Bool()) + val en = Input(Bool()) + val dataIn = Input(UInt.width(32)) + val dataOut = Output(UInt.width(32)) + }) - val stack_mem = Mem(depth, UInt(width = 32)) + val stack_mem = Mem(depth, UInt.width(32)) val sp = Reg(init = UInt(0, width = log2Up(depth + 1))) val out = Reg(init = UInt(0, width = 32)) diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala index d84cd85e..66a06435 100644 --- a/src/test/scala/chiselTests/Tbl.scala +++ b/src/test/scala/chiselTests/Tbl.scala @@ -10,14 +10,14 @@ import chisel3.testers.BasicTester import chisel3.util._ class Tbl(w: Int, n: Int) extends Module { - val io = new Bundle { - val wi = UInt(INPUT, log2Up(n)) - val ri = UInt(INPUT, log2Up(n)) - val we = Bool(INPUT) - val d = UInt(INPUT, w) - val o = UInt(OUTPUT, w) - } - val m = Mem(n, UInt(width = w)) + val io = IO(new Bundle { + val wi = Input(UInt.width(log2Up(n))) + val ri = Input(UInt.width(log2Up(n))) + val we = Input(Bool()) + val d = Input(UInt.width(w)) + val o = Output(UInt.width(w)) + }) + val m = Mem(n, UInt.width(w)) io.o := m(io.ri) when (io.we) { m(io.wi) := io.d diff --git a/src/test/scala/chiselTests/TesterDriverSpec.scala b/src/test/scala/chiselTests/TesterDriverSpec.scala index 2f3e9368..b2e811d9 100644 --- a/src/test/scala/chiselTests/TesterDriverSpec.scala +++ b/src/test/scala/chiselTests/TesterDriverSpec.scala @@ -5,6 +5,7 @@ package chiselTests import chisel3._ import chisel3.testers.BasicTester import chisel3.util._ +//import chisel3.core.ExplicitCompileOptions.Strict /** Extend BasicTester with a simple circuit and finish method. TesterDriver will call the * finish method after the FinishTester's constructor has completed, which will alter the @@ -20,7 +21,7 @@ class FinishTester extends BasicTester { stop() } - val test_wire = Wire(UInt(1, width = test_wire_width)) + val test_wire = Wire(init=UInt(1, test_wire_width)) // though we just set test_wire to 1, the assert below will pass because // the finish will change its value diff --git a/src/test/scala/chiselTests/UIntOps.scala b/src/test/scala/chiselTests/UIntOps.scala index c5069fc4..ad5aecd8 100644 --- a/src/test/scala/chiselTests/UIntOps.scala +++ b/src/test/scala/chiselTests/UIntOps.scala @@ -7,23 +7,23 @@ import org.scalatest._ import chisel3.testers.BasicTester class UIntOps extends Module { - val io = new Bundle { - val a = UInt(INPUT, 16) - val b = UInt(INPUT, 16) - val addout = UInt(OUTPUT, 16) - val subout = UInt(OUTPUT, 16) - val timesout = UInt(OUTPUT, 16) - val divout = UInt(OUTPUT, 16) - val modout = UInt(OUTPUT, 16) - val lshiftout = UInt(OUTPUT, 16) - val rshiftout = UInt(OUTPUT, 16) - val lessout = Bool(OUTPUT) - val greatout = Bool(OUTPUT) - val eqout = Bool(OUTPUT) - val noteqout = Bool(OUTPUT) - val lesseqout = Bool(OUTPUT) - val greateqout = Bool(OUTPUT) - } + val io = IO(new Bundle { + val a = Input(UInt.width(16)) + val b = Input(UInt.width(16)) + val addout = Output(UInt.width(16)) + val subout = Output(UInt.width(16)) + val timesout = Output(UInt.width(16)) + val divout = Output(UInt.width(16)) + val modout = Output(UInt.width(16)) + val lshiftout = Output(UInt.width(16)) + val rshiftout = Output(UInt.width(16)) + val lessout = Output(Bool()) + val greatout = Output(Bool()) + val eqout = Output(Bool()) + val noteqout = Output(Bool()) + val lesseqout = Output(Bool()) + val greateqout = Output(Bool()) + }) val a = io.a val b = io.b @@ -77,18 +77,18 @@ class UIntOpsTester(c: UIntOps) extends Tester(c) { */ class GoodBoolConversion extends Module { - val io = new Bundle { - val u = UInt(1, width = 1).asInput - val b = Bool(OUTPUT) - } + val io = IO(new Bundle { + val u = Input(UInt.width(1)) + val b = Output(Bool()) + }) io.b := io.u.toBool } class BadBoolConversion extends Module { - val io = new Bundle { - val u = UInt(1, width = 5).asInput - val b = Bool(OUTPUT) - } + val io = IO(new Bundle { + val u = Input(UInt.width( 5)) + val b = Output(Bool()) + }) io.b := io.u.toBool } diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala index 7dd80a13..c5447610 100644 --- a/src/test/scala/chiselTests/Vec.scala +++ b/src/test/scala/chiselTests/Vec.scala @@ -8,6 +8,7 @@ import org.scalatest.prop._ import chisel3._ import chisel3.testers.BasicTester import chisel3.util._ +//import chisel3.core.ExplicitCompileOptions.Strict class ValueTester(w: Int, values: List[Int]) extends BasicTester { val v = Vec(values.map(UInt(_, width = w))) // TODO: does this need a Wire? Why no error? @@ -31,7 +32,7 @@ class TabulateTester(n: Int) extends BasicTester { class ShiftRegisterTester(n: Int) extends BasicTester { val (cnt, wrap) = Counter(Bool(true), n*2) - val shifter = Reg(Vec(n, UInt(width = log2Up(n)))) + val shifter = Reg(Vec(n, UInt.width(log2Up(n)))) (shifter, shifter drop 1).zipped.foreach(_ := _) shifter(n-1) := cnt when (cnt >= UInt(n)) { @@ -43,32 +44,6 @@ class ShiftRegisterTester(n: Int) extends BasicTester { } } -class FunBundle extends Bundle { - val stuff = UInt(width = 10) -} - -class ZeroModule extends Module { - val io = new Bundle { - val mem = UInt(width = 10) - val interrupts = Vec(2, Bool()).asInput - val mmio_axi = Vec(0, new FunBundle) - val mmio_ahb = Vec(0, new FunBundle).flip - } - - io.mmio_axi <> io.mmio_ahb - - io.mem := UInt(0) - when (io.interrupts(0)) { io.mem := UInt(1) } - when (io.interrupts(1)) { io.mem := UInt(2) } -} - -class ZeroTester extends BasicTester { - val foo = Module(new ZeroModule) - foo.io.interrupts := Vec.tabulate(2) { _ => Bool(true) } - assert (foo.io.mem === UInt(2)) - stop() -} - class VecSpec extends ChiselPropSpec { property("Vecs should be assignable") { forAll(safeUIntN(8)) { case(w: Int, v: List[Int]) => @@ -83,8 +58,4 @@ class VecSpec extends ChiselPropSpec { property("Regs of vecs should be usable as shift registers") { forAll(smallPosInts) { (n: Int) => assertTesterPasses{ new ShiftRegisterTester(n) } } } - - property("Dual empty Vectors") { - assertTesterPasses{ new ZeroTester } - } } diff --git a/src/test/scala/chiselTests/VectorPacketIO.scala b/src/test/scala/chiselTests/VectorPacketIO.scala index 07779faa..b8e3a154 100644 --- a/src/test/scala/chiselTests/VectorPacketIO.scala +++ b/src/test/scala/chiselTests/VectorPacketIO.scala @@ -19,7 +19,7 @@ import chisel3.util._ * IMPORTANT: The canonical way to initialize a decoupled inteface is still being debated. */ class Packet extends Bundle { - val header = UInt(width = 1) + val header = UInt.width(1) } /** @@ -28,8 +28,8 @@ class Packet extends Bundle { * The problem does not occur if the Vec is taken out */ class VectorPacketIO(n: Int) extends Bundle { - val ins = Vec(n, new DeqIO(new Packet())) - val outs = Vec(n, new EnqIO(new Packet())) + val ins = Vec(n, chisel3.util.DeqIO(new Packet())) + val outs = Vec(n, chisel3.util.EnqIO(new Packet())) } /** @@ -38,10 +38,11 @@ class VectorPacketIO(n: Int) extends Bundle { */ class BrokenVectorPacketModule extends Module { val n = 4 - val io = new VectorPacketIO(n) + val io = IO(new VectorPacketIO(n)) /* the following method of initializing the circuit may change in the future */ - io.outs.foreach(_.init()) + io.ins.foreach(_.nodeq()) + io.outs.foreach(_.noenq()) } class VectorPacketIOUnitTester extends BasicTester { diff --git a/src/test/scala/chiselTests/VendingMachine.scala b/src/test/scala/chiselTests/VendingMachine.scala index f03cb881..00b1e7de 100644 --- a/src/test/scala/chiselTests/VendingMachine.scala +++ b/src/test/scala/chiselTests/VendingMachine.scala @@ -6,10 +6,11 @@ import chisel3._ import chisel3.util._ class VendingMachine extends Module { - val io = new Bundle { - val nickel = Bool(dir = INPUT) - val dime = Bool(dir = INPUT) - val valid = Bool(dir = OUTPUT) } + val io = IO(new Bundle { + val nickel = Input(Bool()) + val dime = Input(Bool()) + val valid = Output(Bool()) + }) val c = UInt(5, width = 3) val sIdle :: s5 :: s10 :: s15 :: sOk :: Nil = Enum(UInt(), 5) val state = Reg(init = sIdle) diff --git a/src/test/scala/chiselTests/When.scala b/src/test/scala/chiselTests/When.scala index 5f3d3e61..6dc2dbac 100644 --- a/src/test/scala/chiselTests/When.scala +++ b/src/test/scala/chiselTests/When.scala @@ -7,12 +7,13 @@ import org.scalatest._ import chisel3._ import chisel3.testers.BasicTester import chisel3.util._ +//import chisel3.core.ExplicitCompileOptions.Strict class WhenTester() extends BasicTester { val cnt = Counter(4) when(Bool(true)) { cnt.inc() } - val out = Wire(UInt(width=3)) + val out = Wire(UInt.width(3)) when(cnt.value === UInt(0)) { out := UInt(1) } .elsewhen (cnt.value === UInt(1)) { @@ -34,7 +35,7 @@ class OverlappedWhenTester() extends BasicTester { val cnt = Counter(4) when(Bool(true)) { cnt.inc() } - val out = Wire(UInt(width=3)) + val out = Wire(UInt.width(3)) when(cnt.value <= UInt(0)) { out := UInt(1) } .elsewhen (cnt.value <= UInt(1)) { |