1 files changed, 21 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/InlineSpec.scala b/src/test/scala/chiselTests/InlineSpec.scala
index 4482d9ec..a2aabdb3 100644
--- a/src/test/scala/chiselTests/InlineSpec.scala
+++ b/src/test/scala/chiselTests/InlineSpec.scala
@@ -3,11 +3,12 @@
 package chiselTests
 
 import chisel3._
-import chisel3.util.experimental.InlineInstance
+import chisel3.util.experimental.{InlineInstance, FlattenInstance}
 import chisel3.internal.firrtl.Circuit
 import firrtl.FirrtlExecutionSuccess
 import firrtl.passes.InlineAnnotation
 import firrtl.annotations.Annotation
+import firrtl.transforms.FlattenAnnotation
 import firrtl.analyses.InstanceGraph
 import firrtl.{ir => fir}
 import firrtl.WDefInstance
@@ -54,4 +55,23 @@ class InlineSpec extends FreeSpec with ChiselRunners with Matchers {
       }
     }
   }
+
+  "Module Flattening" - {
+    class Top extends Module with Internals {
+      val x = Module(new Qux with FlattenInstance)
+      x.io.a := io.a
+    }
+    "should compile to low FIRRTL" - {
+      Driver.execute(Array("-X", "low", "--target-dir", "test_run_dir"), () => new Top) match {
+        case ChiselExecutionSuccess(Some(chiselCircuit), chirrtl, Some(firrtlResult: FirrtlExecutionSuccess)) =>
+          "emitting ONE FlattenAnnotation at the CHIRRTL level" in {
+            chiselCircuit.annotations.map(_.toFirrtl).collect{ case a: FlattenAnnotation => a }.size should be (1)
+          }
+          "low FIRRTL should contain instance x only" in {
+            val instances = collectInstances(firrtlResult.circuitState.circuit, Some("Top")).toSet
+            Set("Top", "Top.x") should be (instances)
+          }
+      }
+    }
+  }
 }