4 files changed, 2 insertions, 4 deletions
diff --git a/src/test/scala/chiselTests/CloneModuleSpec.scala b/src/test/scala/chiselTests/CloneModuleSpec.scala
index 9a637df9..bef29fce 100644
--- a/src/test/scala/chiselTests/CloneModuleSpec.scala
+++ b/src/test/scala/chiselTests/CloneModuleSpec.scala
@@ -4,7 +4,7 @@ package chiselTests
 
 import chisel3._
 import chisel3.util.{Queue, EnqIO, DeqIO, QueueIO, log2Ceil}
-import chisel3.experimental.{CloneModuleAsRecord, MultiIOModule, withClockAndReset}
+import chisel3.experimental.{CloneModuleAsRecord, MultiIOModule}
 import chisel3.testers.BasicTester
 import org.scalatest._
 import org.scalatest.prop._
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index b3d1899c..a973412e 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -3,7 +3,6 @@
 package chiselTests
 
 import chisel3._
-import chisel3.experimental.{withClock, withReset}
 
 class SimpleIO extends Bundle {
   val in  = Input(UInt(32.W))
diff --git a/src/test/scala/chiselTests/MultiClockSpec.scala b/src/test/scala/chiselTests/MultiClockSpec.scala
index 6e84c9b2..770a9e9a 100644
--- a/src/test/scala/chiselTests/MultiClockSpec.scala
+++ b/src/test/scala/chiselTests/MultiClockSpec.scala
@@ -3,7 +3,6 @@
 package chiselTests
 
 import chisel3._
-import chisel3.experimental.{withClockAndReset, withClock, withReset}
 import chisel3.util.Counter
 import chisel3.testers.BasicTester
 
diff --git a/src/test/scala/chiselTests/RawModuleSpec.scala b/src/test/scala/chiselTests/RawModuleSpec.scala
index b864a669..88b53457 100644
--- a/src/test/scala/chiselTests/RawModuleSpec.scala
+++ b/src/test/scala/chiselTests/RawModuleSpec.scala
@@ -3,7 +3,7 @@
 package chiselTests
 
 import chisel3._
-import chisel3.experimental.{RawModule, withClockAndReset}
+import chisel3.experimental.RawModule
 import chisel3.testers.BasicTester
 
 class UnclockedPlusOne extends RawModule {