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-rw-r--r--src/test/scala/chiselTests/BulkConnectSpec.scala106
-rw-r--r--src/test/scala/chiselTests/BundleSpec.scala1
-rw-r--r--src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala2
-rw-r--r--src/test/scala/chiselTests/MixedVecSpec.scala16
-rw-r--r--src/test/scala/chiselTests/Module.scala9
-rw-r--r--src/test/scala/chiselTests/RecordSpec.scala19
-rw-r--r--src/test/scala/chiselTests/UIntOps.scala18
-rw-r--r--src/test/scala/chiselTests/VecLiteralSpec.scala5
-rw-r--r--src/test/scala/chiselTests/experimental/DataView.scala8
-rw-r--r--src/test/scala/chiselTests/experimental/hierarchy/Annotations.scala10
-rw-r--r--src/test/scala/chiselTests/experimental/hierarchy/DefinitionSpec.scala33
-rw-r--r--src/test/scala/chiselTests/experimental/hierarchy/Examples.scala19
-rw-r--r--src/test/scala/chiselTests/experimental/hierarchy/InstanceSpec.scala91
-rw-r--r--src/test/scala/chiselTests/util/experimental/TruthTableSpec.scala24
14 files changed, 350 insertions, 11 deletions
diff --git a/src/test/scala/chiselTests/BulkConnectSpec.scala b/src/test/scala/chiselTests/BulkConnectSpec.scala
new file mode 100644
index 00000000..463122bd
--- /dev/null
+++ b/src/test/scala/chiselTests/BulkConnectSpec.scala
@@ -0,0 +1,106 @@
+package chiselTests
+
+import chisel3._
+import chisel3.util.Decoupled
+import chisel3.stage.ChiselStage
+import chisel3.testers.BasicTester
+
+class BulkConnectSpec extends ChiselPropSpec {
+ property("Chisel connects should emit FIRRTL bulk connects when possible") {
+ val chirrtl = ChiselStage.emitChirrtl(new Module {
+ val io = IO(new Bundle {
+ val inMono = Input(Vec(4, UInt(8.W)))
+ val outMono = Output(Vec(4, UInt(8.W)))
+ val inBi = Input(Vec(4, UInt(8.W)))
+ val outBi = Output(Vec(4, UInt(8.W)))
+ })
+ io.outMono := io.inMono
+ io.outBi <> io.inBi
+ })
+ chirrtl should include("io.outMono <= io.inMono")
+ chirrtl should include("io.outBi <= io.inBi")
+ }
+
+ property("Chisel connects should not emit FIRRTL bulk connects for Stringly-typed connections") {
+ object Foo {
+ import Chisel._
+ // Chisel._ bundle
+ class BundleParent extends Bundle {
+ val foo = UInt(width = 8)
+ }
+ class BundleChild extends BundleParent {
+ val bar = UInt(width = 8)
+ }
+ }
+
+ import Foo._
+
+ // chisel3._ bundle
+ class MyBundle(child: Boolean) extends Bundle {
+ val fizz = UInt(8.W)
+ val buzz = if (child) new BundleChild else new BundleParent
+ }
+
+ val chirrtl = ChiselStage.emitChirrtl(new Module {
+ // Checking MonoConnect
+ val in = IO(Input(new MyBundle(true)))
+ val out = IO(Output(new MyBundle(false)))
+ out := in
+
+ // Checking BulkConnect (with Decoupled)
+ val enq = IO(Flipped(Decoupled(new BundleChild)))
+ val deq = IO(Decoupled(new BundleParent))
+ deq <> enq
+ })
+
+ chirrtl should include("out.buzz.foo <= in.buzz.foo")
+ chirrtl shouldNot include("deq <= enq")
+ }
+
+ property("Chisel connects should not emit FIRRTL bulk connects between differing FIRRTL types") {
+ val chirrtl = ChiselStage.emitChirrtl(new Module {
+ val in = IO(Flipped(new Bundle {
+ val foo = Flipped(new Bundle {
+ val bar = Input(UInt(8.W))
+ })
+ }))
+ val out = IO(Output(new Bundle {
+ val foo = new Bundle {
+ val bar = UInt(8.W)
+ }
+ }))
+ // Both of these connections are legal in Chisel, but in and out do not have the same type
+ out := in
+ out <> in
+ })
+ // out <- in is illegal FIRRTL
+ chirrtl should include("out.foo.bar <= in.foo.bar")
+ }
+
+ property("Chisel connects should not emit a FIRRTL bulk connect for a bidirectional MonoConnect") {
+ val chirrtl = ChiselStage.emitChirrtl(new Module {
+ val enq = IO(Flipped(Decoupled(UInt(8.W))))
+ val deq = IO(Decoupled(UInt(8.W)))
+
+ // Implicitly create a MonoConnect from enq to a wire
+ // enq is a Decoupled and so has input/output signals
+ // We should not bulk connect in this case
+ val wire = WireDefault(enq)
+ dontTouch(wire)
+ deq <> enq
+ })
+
+ chirrtl shouldNot include("wire <= enq")
+ chirrtl should include("deq <= enq")
+ }
+
+ property("MonoConnect should bulk connect undirectioned internal wires") {
+ val chirrtl = ChiselStage.emitChirrtl(new Module {
+ val io = IO(new Bundle {})
+ val w1 = Wire(Vec(2, UInt(8.W)))
+ val w2 = Wire(Vec(2, UInt(8.W)))
+ w2 := w1
+ })
+ chirrtl should include("w2 <= w1")
+ }
+}
diff --git a/src/test/scala/chiselTests/BundleSpec.scala b/src/test/scala/chiselTests/BundleSpec.scala
index 5dcbbefa..2d34b263 100644
--- a/src/test/scala/chiselTests/BundleSpec.scala
+++ b/src/test/scala/chiselTests/BundleSpec.scala
@@ -3,6 +3,7 @@
package chiselTests
import chisel3._
+import chisel3.util.Decoupled
import chisel3.stage.ChiselStage
import chisel3.testers.BasicTester
diff --git a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala
index 8210b120..70dcda48 100644
--- a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala
+++ b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala
@@ -74,7 +74,7 @@ object Chisel3Components {
class Chisel3ModuleChiselRecordB extends Chisel3PassthroughModule(Flipped(new ChiselRecord))
}
-class CompatibiltyInteroperabilitySpec extends ChiselFlatSpec {
+class CompatibilityInteroperabilitySpec extends ChiselFlatSpec {
"Modules defined in the Chisel._" should "successfully bulk connect in chisel3._" in {
import chisel3._
diff --git a/src/test/scala/chiselTests/MixedVecSpec.scala b/src/test/scala/chiselTests/MixedVecSpec.scala
index 16efafd4..ee19d653 100644
--- a/src/test/scala/chiselTests/MixedVecSpec.scala
+++ b/src/test/scala/chiselTests/MixedVecSpec.scala
@@ -280,4 +280,20 @@ class MixedVecSpec extends ChiselPropSpec with Utils {
})
}
}
+
+ property("MixedVec connections should emit FIRRTL bulk connects when possible") {
+ val chirrtl = ChiselStage.emitChirrtl(new Module {
+ val io = IO(new Bundle {
+ val inMono = Input(MixedVec(Seq(UInt(8.W), UInt(16.W), UInt(4.W), UInt(7.W))))
+ val outMono = Output(MixedVec(Seq(UInt(8.W), UInt(16.W), UInt(4.W), UInt(7.W))))
+ val inBi = Input(MixedVec(Seq(UInt(8.W), UInt(16.W), UInt(4.W), UInt(7.W))))
+ val outBi = Output(MixedVec(Seq(UInt(8.W), UInt(16.W), UInt(4.W), UInt(7.W))))
+ })
+ // Explicit upcast avoids weird issue where Scala 2.12 overloading resolution calls version of := accepting Seq[T] instead of normal Data version
+ io.outMono := (io.inMono: Data)
+ io.outBi <> io.inBi
+ })
+ chirrtl should include("io.outMono <= io.inMono @[MixedVecSpec.scala")
+ chirrtl should include("io.outBi <= io.inBi @[MixedVecSpec.scala")
+ }
}
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index 13dbe1e9..b0fece3b 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -18,6 +18,8 @@ class SimpleIO extends Bundle {
class PlusOne extends Module {
val io = IO(new SimpleIO)
+ val myReg = RegInit(0.U(8.W))
+ dontTouch(myReg)
io.out := io.in + 1.asUInt
}
@@ -267,6 +269,13 @@ class ModuleSpec extends ChiselPropSpec with Utils {
property("getVerilogString(new PlusOne() should produce a valid Verilog string") {
val s = getVerilogString(new PlusOne())
assert(s.contains("assign io_out = io_in + 32'h1"))
+ assert(s.contains("RANDOMIZE_REG_INIT"))
+ }
+
+ property("getVerilogString(new PlusOne() should produce a valid Verilog string with arguments") {
+ val s = getVerilogString(new PlusOne(), Array("--emission-options=disableRegisterRandomization"))
+ assert(s.contains("assign io_out = io_in + 32'h1"))
+ assert(!s.contains("RANDOMIZE_REG_INIT"))
}
property("emitVerilog((new PlusOne()..) shall produce a valid Verilog file in a subfolder") {
diff --git a/src/test/scala/chiselTests/RecordSpec.scala b/src/test/scala/chiselTests/RecordSpec.scala
index da3840dd..30b55812 100644
--- a/src/test/scala/chiselTests/RecordSpec.scala
+++ b/src/test/scala/chiselTests/RecordSpec.scala
@@ -27,6 +27,17 @@ trait RecordSpecUtils {
io.out <> io.in
}
+ class ConnectionTestModule(output: => Record, input: => Record) extends Module {
+ val io = IO(new Bundle {
+ val inMono = Input(input)
+ val outMono = Output(output)
+ val inBi = Input(input)
+ val outBi = Output(output)
+ })
+ io.outMono := io.inMono
+ io.outBi <> io.inBi
+ }
+
class RecordSerializationTest extends BasicTester {
val recordType = new CustomBundle("fizz" -> UInt(16.W), "buzz" -> UInt(16.W))
val record = Wire(recordType)
@@ -110,6 +121,14 @@ class RecordSpec extends ChiselFlatSpec with RecordSpecUtils with Utils {
ChiselStage.elaborate { new MyModule(new MyBundle, fooBarType) }
}
+ they should "emit FIRRTL bulk connects when possible" in {
+ val chirrtl = (new ChiselStage).emitChirrtl(
+ gen = new ConnectionTestModule(fooBarType, fooBarType)
+ )
+ chirrtl should include("io.outMono <= io.inMono @[RecordSpec.scala")
+ chirrtl should include("io.outBi <= io.inBi @[RecordSpec.scala")
+ }
+
they should "not allow aliased fields" in {
class AliasedFieldRecord extends Record {
val foo = UInt(8.W)
diff --git a/src/test/scala/chiselTests/UIntOps.scala b/src/test/scala/chiselTests/UIntOps.scala
index 5fb86001..0010e9ac 100644
--- a/src/test/scala/chiselTests/UIntOps.scala
+++ b/src/test/scala/chiselTests/UIntOps.scala
@@ -199,6 +199,24 @@ class UIntOpsSpec extends ChiselPropSpec with Matchers with Utils {
a[Exception] should be thrownBy extractCause[Exception] { ChiselStage.elaborate(new BadBoolConversion) }
}
+ property("Out-of-bounds extraction from known-width UInts") {
+ a[ChiselException] should be thrownBy extractCause[ChiselException] {
+ ChiselStage.elaborate(new RawModule {
+ val u = IO(Input(UInt(2.W)))
+ u(2, 1)
+ })
+ }
+ }
+
+ property("Out-of-bounds single-bit extraction from known-width UInts") {
+ a[ChiselException] should be thrownBy extractCause[ChiselException] {
+ ChiselStage.elaborate(new RawModule {
+ val u = IO(Input(UInt(2.W)))
+ u(2)
+ })
+ }
+ }
+
property("UIntOps should elaborate") {
ChiselStage.elaborate { new UIntOps }
}
diff --git a/src/test/scala/chiselTests/VecLiteralSpec.scala b/src/test/scala/chiselTests/VecLiteralSpec.scala
index 228f409b..fa97a8c8 100644
--- a/src/test/scala/chiselTests/VecLiteralSpec.scala
+++ b/src/test/scala/chiselTests/VecLiteralSpec.scala
@@ -434,7 +434,7 @@ class VecLiteralSpec extends ChiselFreeSpec with Utils {
exc.getMessage should include("field 0 specified with non-literal value UInt")
}
- "vec literals are instantiated on connect" in {
+ "vec literals are instantiated on connect and are not bulk connected" in {
class VecExample5 extends RawModule {
val out = IO(Output(Vec(2, UInt(4.W))))
val bundle = Vec(2, UInt(4.W)).Lit(
@@ -463,13 +463,12 @@ class VecLiteralSpec extends ChiselFreeSpec with Utils {
out := bundle
}
- "vec literals can contain bundles" in {
+ "vec literals can contain bundles and should not be bulk connected" in {
val chirrtl = (new chisel3.stage.ChiselStage).emitChirrtl(new VecExample, args = Array("--full-stacktrace"))
chirrtl should include("""out[0].bar <= UInt<5>("h16")""")
chirrtl should include("""out[0].foo <= UInt<6>("h2a")""")
chirrtl should include("""out[1].bar <= UInt<2>("h3")""")
chirrtl should include("""out[1].foo <= UInt<3>("h7")""")
-
}
"vec literals can have bundle children" in {
diff --git a/src/test/scala/chiselTests/experimental/DataView.scala b/src/test/scala/chiselTests/experimental/DataView.scala
index 5ef062fa..0285a524 100644
--- a/src/test/scala/chiselTests/experimental/DataView.scala
+++ b/src/test/scala/chiselTests/experimental/DataView.scala
@@ -103,8 +103,8 @@ class DataViewSpec extends ChiselFlatSpec {
buzz.viewAs[MyBundle] := in
}
val chirrtl = ChiselStage.emitChirrtl(new MyModule)
- chirrtl should include("fizz.foo <= in.foo")
- chirrtl should include("buzz.foo <= in.foo")
+ chirrtl should include("fizz <= in")
+ chirrtl should include("buzz <= in")
}
it should "handle viewing Vecs as their same concrete type" in {
@@ -116,8 +116,8 @@ class DataViewSpec extends ChiselFlatSpec {
buzz.viewAs[Vec[UInt]] := in
}
val chirrtl = ChiselStage.emitChirrtl(new MyModule)
- chirrtl should include("fizz[0] <= in[0]")
- chirrtl should include("buzz[0] <= in[0]")
+ chirrtl should include("fizz <= in")
+ chirrtl should include("buzz <= in")
}
it should "handle viewing Vecs as Bundles and vice versa" in {
diff --git a/src/test/scala/chiselTests/experimental/hierarchy/Annotations.scala b/src/test/scala/chiselTests/experimental/hierarchy/Annotations.scala
index 2c1d2e9e..ec71fe09 100644
--- a/src/test/scala/chiselTests/experimental/hierarchy/Annotations.scala
+++ b/src/test/scala/chiselTests/experimental/hierarchy/Annotations.scala
@@ -4,10 +4,11 @@ package chiselTests.experimental.hierarchy
import _root_.firrtl.annotations._
import chisel3.experimental.{annotate, BaseModule}
-import chisel3.Data
+import chisel3.{Data, MemBase}
import chisel3.experimental.hierarchy.{Definition, Hierarchy, Instance}
-object Annotations {
+// These annotations exist purely for testing purposes
+private[hierarchy] object Annotations {
case class MarkAnnotation(target: IsMember, tag: String) extends SingleTargetAnnotation[IsMember] {
def duplicate(n: IsMember): Annotation = this.copy(target = n)
}
@@ -19,7 +20,12 @@ object Annotations {
extends chisel3.experimental.ChiselAnnotation {
def toFirrtl = if (isAbsolute) MarkAnnotation(d.toAbsoluteTarget, tag) else MarkAnnotation(d.toTarget, tag)
}
+ case class MarkChiselMemAnnotation[T <: Data](m: MemBase[T], tag: String, isAbsolute: Boolean)
+ extends chisel3.experimental.ChiselAnnotation {
+ def toFirrtl = if (isAbsolute) MarkAnnotation(m.toAbsoluteTarget, tag) else MarkAnnotation(m.toTarget, tag)
+ }
def mark(d: Data, tag: String): Unit = annotate(MarkChiselAnnotation(d, tag, false))
+ def mark[T <: Data](d: MemBase[T], tag: String): Unit = annotate(MarkChiselMemAnnotation(d, tag, false))
def mark[B <: BaseModule](d: Hierarchy[B], tag: String): Unit = annotate(MarkChiselHierarchyAnnotation(d, tag, true))
def amark(d: Data, tag: String): Unit = annotate(MarkChiselAnnotation(d, tag, true))
def amark[B <: BaseModule](d: Hierarchy[B], tag: String): Unit = annotate(MarkChiselHierarchyAnnotation(d, tag, true))
diff --git a/src/test/scala/chiselTests/experimental/hierarchy/DefinitionSpec.scala b/src/test/scala/chiselTests/experimental/hierarchy/DefinitionSpec.scala
index 63beb394..6ff4a3eb 100644
--- a/src/test/scala/chiselTests/experimental/hierarchy/DefinitionSpec.scala
+++ b/src/test/scala/chiselTests/experimental/hierarchy/DefinitionSpec.scala
@@ -329,6 +329,39 @@ class DefinitionSpec extends ChiselFunSpec with Utils {
annos should contain(MarkAnnotation("~Top|HasEither>x".rt, "xright"))
annos should contain(MarkAnnotation("~Top|HasEither>y".rt, "yleft"))
}
+ it("3.12: should work on tuple2") {
+ class Top() extends Module {
+ val i = Definition(new HasTuple2())
+ mark(i.xy._1, "x")
+ mark(i.xy._2, "y")
+ }
+ val (_, annos) = getFirrtlAndAnnos(new Top)
+ annos should contain(MarkAnnotation("~Top|HasTuple2>x".rt, "x"))
+ annos should contain(MarkAnnotation("~Top|HasTuple2>y".rt, "y"))
+ }
+ it("3.13: should work on Mems/SyncReadMems") {
+ class Top() extends Module {
+ val i = Definition(new HasMems())
+ mark(i.mem, "Mem")
+ mark(i.syncReadMem, "SyncReadMem")
+ }
+ val (_, annos) = getFirrtlAndAnnos(new Top)
+ annos should contain(MarkAnnotation("~Top|HasMems>mem".rt, "Mem"))
+ annos should contain(MarkAnnotation("~Top|HasMems>syncReadMem".rt, "SyncReadMem"))
+ }
+ it("3.14: should not create memory ports") {
+ class Top() extends Module {
+ val i = Definition(new HasMems())
+ i.mem(0) := 100.U // should be illegal!
+ }
+ val failure = intercept[ChiselException] {
+ getFirrtlAndAnnos(new Top)
+ }
+ assert(
+ failure.getMessage ==
+ "Cannot create a memory port in a different module (Top) than where the memory is (HasMems)."
+ )
+ }
}
describe("4: toDefinition") {
it("4.0: should work on modules") {
diff --git a/src/test/scala/chiselTests/experimental/hierarchy/Examples.scala b/src/test/scala/chiselTests/experimental/hierarchy/Examples.scala
index 5b78b7cc..fa26cbde 100644
--- a/src/test/scala/chiselTests/experimental/hierarchy/Examples.scala
+++ b/src/test/scala/chiselTests/experimental/hierarchy/Examples.scala
@@ -47,6 +47,13 @@ object Examples {
val addOneDef = Seq.fill(3)(Definition(new AddOne))
out := in + 1.U
}
+ @instantiable
+ class AddOneBlackBox extends BlackBox {
+ @public val io = IO(new Bundle {
+ val in = Input(UInt(32.W))
+ val out = Output(UInt(32.W))
+ })
+ }
@instantiable
class AddTwo extends Module {
@@ -200,6 +207,12 @@ object Examples {
@public val y: Either[Bool, UInt] = Left(Wire(Bool()).suggestName("y"))
}
@instantiable
+ class HasTuple2() extends Module {
+ val x = Wire(UInt(3.W))
+ val y = Wire(Bool())
+ @public val xy = (x, y)
+ }
+ @instantiable
class HasVec() extends Module {
@public val x = VecInit(1.U, 2.U, 3.U)
}
@@ -252,4 +265,10 @@ object Examples {
val i10 = Instance(tpDef1)
val i11 = Instance(tpDef1)
}
+
+ @instantiable
+ class HasMems() extends Module {
+ @public val mem = Mem(8, UInt(32.W))
+ @public val syncReadMem = SyncReadMem(8, UInt(32.W))
+ }
}
diff --git a/src/test/scala/chiselTests/experimental/hierarchy/InstanceSpec.scala b/src/test/scala/chiselTests/experimental/hierarchy/InstanceSpec.scala
index 45d1f85f..8d8f7ea5 100644
--- a/src/test/scala/chiselTests/experimental/hierarchy/InstanceSpec.scala
+++ b/src/test/scala/chiselTests/experimental/hierarchy/InstanceSpec.scala
@@ -43,6 +43,29 @@ class InstanceSpec extends ChiselFunSpec with Utils {
val (chirrtl, _) = getFirrtlAndAnnos(new Top)
chirrtl.serialize should include("inst i0 of AddOne")
}
+ it("0.3: BlackBoxes should be supported") {
+ class Top extends Module {
+ val in = IO(Input(UInt(32.W)))
+ val out = IO(Output(UInt(32.W)))
+ val io = IO(new Bundle {
+ val in = Input(UInt(32.W))
+ val out = Output(UInt(32.W))
+ })
+ val definition = Definition(new AddOneBlackBox)
+ val i0 = Instance(definition)
+ val i1 = Instance(definition)
+ i0.io.in := in
+ out := i0.io.out
+ io <> i1.io
+ }
+ val chirrtl = getFirrtlAndAnnos(new Top)._1.serialize
+ chirrtl should include("inst i0 of AddOneBlackBox")
+ chirrtl should include("inst i1 of AddOneBlackBox")
+ chirrtl should include("i0.in <= in")
+ chirrtl should include("out <= i0.out")
+ chirrtl should include("i1.in <= io.in")
+ chirrtl should include("io.out <= i1.out")
+ }
}
describe("1: Annotations on instances in same chisel compilation") {
it("1.0: should work on a single instance, annotating the instance") {
@@ -298,7 +321,18 @@ class InstanceSpec extends ChiselFunSpec with Utils {
annos should contain(MarkAnnotation("~Top|Top/i:HasEither>x".rt, "xright"))
annos should contain(MarkAnnotation("~Top|Top/i:HasEither>y".rt, "yleft"))
}
- it("3.12: should properly support val modifiers") {
+ it("3.12: should work on tuple2") {
+ class Top() extends Module {
+ val i = Instance(Definition(new HasTuple2()))
+ mark(i.xy._1, "x")
+ mark(i.xy._2, "y")
+ }
+ val (_, annos) = getFirrtlAndAnnos(new Top)
+ annos should contain(MarkAnnotation("~Top|Top/i:HasTuple2>x".rt, "x"))
+ annos should contain(MarkAnnotation("~Top|Top/i:HasTuple2>y".rt, "y"))
+ }
+
+ it("3.13: should properly support val modifiers") {
class SupClass extends Module {
val value = 10
val overriddenVal = 10
@@ -320,6 +354,16 @@ class InstanceSpec extends ChiselFunSpec with Utils {
@public override final lazy val y: Int = 4
}
}
+ it("3.13: should work with Mems/SyncReadMems") {
+ class Top() extends Module {
+ val i = Instance(Definition(new HasMems()))
+ mark(i.mem, "Mem")
+ mark(i.syncReadMem, "SyncReadMem")
+ }
+ val (_, annos) = getFirrtlAndAnnos(new Top)
+ annos should contain(MarkAnnotation("~Top|Top/i:HasMems>mem".rt, "Mem"))
+ annos should contain(MarkAnnotation("~Top|Top/i:HasMems>syncReadMem".rt, "SyncReadMem"))
+ }
}
describe("4: toInstance") {
it("4.0: should work on modules") {
@@ -695,6 +739,51 @@ class InstanceSpec extends ChiselFunSpec with Utils {
annos should contain(e)
}
}
+
+ it("7.4: should work on Views of BlackBoxes") {
+ @instantiable
+ class MyBlackBox extends BlackBox {
+ @public val io = IO(new Bundle {
+ val in = Input(UInt(8.W))
+ val out = Output(UInt(8.W))
+ })
+ @public val innerView = io.viewAs
+ @public val foo = io.in.viewAs[UInt]
+ @public val bar = io.out.viewAs[UInt]
+ }
+ class Top extends RawModule {
+ val foo = IO(Input(UInt(8.W)))
+ val bar = IO(Output(UInt(8.W)))
+ val i = Instance(Definition(new MyBlackBox))
+ val outerView = i.io.viewAs
+ i.foo := foo
+ bar := i.bar
+ mark(i.foo, "i.foo")
+ mark(i.bar, "i.bar")
+ mark(i.innerView.in, "i.innerView.in")
+ mark(outerView.out, "outerView.out")
+ }
+ val inst = "~Top|Top/i:MyBlackBox"
+ val expectedAnnos = List(
+ s"$inst>in".rt -> "i.foo",
+ s"$inst>out".rt -> "i.bar",
+ s"$inst>in".rt -> "i.innerView.in",
+ s"$inst>out".rt -> "outerView.out"
+ )
+ val expectedLines = List(
+ "i.in <= foo",
+ "bar <= i.out"
+ )
+ val (chirrtl, annos) = getFirrtlAndAnnos(new Top)
+ val text = chirrtl.serialize
+ for (line <- expectedLines) {
+ text should include(line)
+ }
+ for (e <- expectedAnnos.map(MarkAnnotation.tupled)) {
+ annos should contain(e)
+ }
+ }
+
}
describe("8: @instantiable and @public should compose with CloneModuleAsRecord") {
diff --git a/src/test/scala/chiselTests/util/experimental/TruthTableSpec.scala b/src/test/scala/chiselTests/util/experimental/TruthTableSpec.scala
index 2ef316bb..fa2c6f08 100644
--- a/src/test/scala/chiselTests/util/experimental/TruthTableSpec.scala
+++ b/src/test/scala/chiselTests/util/experimental/TruthTableSpec.scala
@@ -80,4 +80,28 @@ class TruthTableSpec extends AnyFlatSpec {
}
assert(chisel3.stage.ChiselStage.emitChirrtl(new Foo) == chisel3.stage.ChiselStage.emitChirrtl(new Foo))
}
+ "TruthTable" should "accept unknown input width" in {
+ val t = TruthTable(
+ Seq(
+ BitPat(0.U) -> BitPat.dontCare(1),
+ BitPat(1.U) -> BitPat.dontCare(1),
+ BitPat(2.U) -> BitPat.dontCare(1),
+ BitPat(3.U) -> BitPat.dontCare(1),
+ BitPat(4.U) -> BitPat.dontCare(1),
+ BitPat(5.U) -> BitPat.dontCare(1),
+ BitPat(6.U) -> BitPat.dontCare(1),
+ BitPat(7.U) -> BitPat.dontCare(1)
+ ),
+ BitPat.N(1)
+ )
+ assert(t.toString contains "000->?")
+ assert(t.toString contains "001->?")
+ assert(t.toString contains "010->?")
+ assert(t.toString contains "011->?")
+ assert(t.toString contains "100->?")
+ assert(t.toString contains "101->?")
+ assert(t.toString contains "110->?")
+ assert(t.toString contains "111->?")
+ assert(t.toString contains " 0")
+ }
}
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-31 15:58:51 +0000