1 files changed, 4 insertions, 3 deletions
diff --git a/src/test/scala/chiselTests/Harness.scala b/src/test/scala/chiselTests/Harness.scala
index 8a12cd7b..1da3d166 100644
--- a/src/test/scala/chiselTests/Harness.scala
+++ b/src/test/scala/chiselTests/Harness.scala
@@ -6,9 +6,10 @@ import chisel3.testers.BasicTester
 import org.scalatest._
 import org.scalatest.prop._
 import java.io.File
+import firrtl.util.BackendCompilationUtilities
 
 class HarnessSpec extends ChiselPropSpec
-  with chisel3.BackendCompilationUtilities {
+  with BackendCompilationUtilities {
 
   def makeTrivialVerilog: (File => File) = makeHarness((prefix: String) => s"""
 module ${prefix};
@@ -55,13 +56,13 @@ void vl_finish(const char* filename, int linenum, const char* hier) {
     */
   def simpleHarnessBackend(make: File => File): (File, String) = {
     val target = "test"
-    val path = createTempDirectory(target)
+    val path = createTestDirectory(target)
     val fname = new File(path, target)
 
     val cppHarness = makeCppHarness(fname)
 
     make(fname)
-    verilogToCpp(target, target, path, Seq(), cppHarness).!
+    verilogToCpp(target, path, Seq(), cppHarness).!
     cppToExe(target, path).!
     (path, target)
   }