2 files changed, 78 insertions, 10 deletions

diff --git a/src/test/resources/BlackBoxTest.v b/src/test/resources/BlackBoxTest.v
index e57d2852..910b09ff 100644
--- a/src/test/resources/BlackBoxTest.v
+++ b/src/test/resources/BlackBoxTest.v
@@ -1,17 +1,34 @@
 module BlackBoxInverter(
-    input  [0:0] clk,
-    input  [0:0] reset,
-    output [0:0] io_in,
-    output [0:0] io_out
+    input  [0:0] in,
+    output [0:0] out
 );
-  assign io_out = !io_in;
+  assign out = !in;
 endmodule
 
 module BlackBoxPassthrough(
-    input  [0:0] clk,
-    input  [0:0] reset,
-    output [0:0] io_in,
-    output [0:0] io_out
+    input  [0:0] in,
+    output [0:0] out
 );
-  assign io_out = io_in;
+  assign out = in;
+endmodule
+
+module BlackBoxRegister(
+    input  [0:0] clock,
+    input  [0:0] in,
+    output [0:0] out
+);
+  reg [0:0] register;
+  always @(posedge clock) begin
+    register <= in;
+  end
+  assign out = register;
+endmodule
+
+module BlackBoxConstant #(
+  parameter int WIDTH=1,
+  parameter int VALUE=1
+) (
+  output [WIDTH-1:0] out
+);
+  assign out = VALUE;
 endmodule
diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala
index 574a6335..ca94087c 100644
--- a/src/test/scala/chiselTests/BlackBox.scala
+++ b/src/test/scala/chiselTests/BlackBox.scala
@@ -21,6 +21,14 @@ class BlackBoxPassthrough extends BlackBox {
   }
 }
 
+class BlackBoxRegister extends BlackBox {
+  val io = new Bundle() {
+    val clock = Clock().asInput
+    val in = Bool(INPUT)
+    val out = Bool(OUTPUT)
+  }
+}
+
 class BlackBoxTester extends BasicTester {
   val blackBoxPos = Module(new BlackBoxInverter)
   val blackBoxNeg = Module(new BlackBoxInverter)
@@ -56,6 +64,45 @@ class MultiBlackBoxTester extends BasicTester {
   stop()
 }
 
+class BlackBoxWithClockTester extends BasicTester {
+  val blackBox = Module(new BlackBoxRegister)
+  val model = Reg(Bool())
+
+  val (cycles, end) = Counter(Bool(true), 15)
+
+  val impetus = cycles(0)
+  blackBox.io.clock := clock
+  blackBox.io.in := impetus
+  model := impetus
+
+  when(cycles > UInt(0)) {
+    assert(blackBox.io.out === model)
+  }
+  when(end) { stop() }
+}
+
+/*
+// Must determine how to handle parameterized Verilog
+class BlackBoxConstant(value: Int) extends BlackBox {
+  val io = new Bundle() {
+    val out = UInt(width=log2Up(value)).asOutput
+  }
+  override val name = s"#(WIDTH=${log2Up(value)},VALUE=$value) "
+}
+
+class BlackBoxWithParamsTester extends BasicTester {
+  val blackBoxOne  = Module(new BlackBoxConstant(1))
+  val blackBoxFour = Module(new BlackBoxConstant(4))
+
+  val (cycles, end) = Counter(Bool(true), 4)
+
+  assert(blackBoxOne.io.out  === UInt(1))
+  assert(blackBoxFour.io.out === UInt(4))
+
+  when(end) { stop() }
+}
+*/
+
 class BlackBoxSpec extends ChiselFlatSpec {
   "A BlackBoxed inverter" should "work" in {
     assertTesterPasses({ new BlackBoxTester },
@@ -65,4 +112,8 @@ class BlackBoxSpec extends ChiselFlatSpec {
     assertTesterPasses({ new MultiBlackBoxTester },
         Seq("/BlackBoxTest.v"))
   }
+  "A BlackBoxed register" should "work" in {
+    assertTesterPasses({ new BlackBoxWithClockTester },
+        Seq("/BlackBoxTest.v"))
+  }
 }