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-rw-r--r--src/test/scala/chiselTests/BitwiseOps.scala8
-rw-r--r--src/test/scala/chiselTests/BundleWire.scala4
-rw-r--r--src/test/scala/chiselTests/ComplexAssign.scala6
-rw-r--r--src/test/scala/chiselTests/DeqIOSpec.scala2
-rw-r--r--src/test/scala/chiselTests/GCD.scala4
-rw-r--r--src/test/scala/chiselTests/MultiAssign.scala2
-rw-r--r--src/test/scala/chiselTests/Reg.scala6
-rw-r--r--src/test/scala/chiselTests/Risc.scala12
-rw-r--r--src/test/scala/chiselTests/Stack.scala2
-rw-r--r--src/test/scala/chiselTests/Tbl.scala10
-rw-r--r--src/test/scala/chiselTests/UIntOps.scala2
-rw-r--r--src/test/scala/chiselTests/Vec.scala8
-rw-r--r--src/test/scala/chiselTests/VectorPacketIO.scala2
-rw-r--r--src/test/scala/chiselTests/When.scala4
14 files changed, 36 insertions, 36 deletions
diff --git a/src/test/scala/chiselTests/BitwiseOps.scala b/src/test/scala/chiselTests/BitwiseOps.scala
index 08999a1b..0aaa3c57 100644
--- a/src/test/scala/chiselTests/BitwiseOps.scala
+++ b/src/test/scala/chiselTests/BitwiseOps.scala
@@ -11,10 +11,10 @@ class BitwiseOpsTester(w: Int, _a: Int, _b: Int) extends BasicTester {
val mask = (1 << w) - 1
val a = UInt(_a, w)
val b = UInt(_b, w)
- assert(~a === UInt(mask & ~_a))
- assert((a & b) === UInt(_a & _b))
- assert((a | b) === UInt(_a | _b))
- assert((a ^ b) === UInt(_a ^ _b))
+ assert(~a === UInt.Lit(mask & ~_a))
+ assert((a & b) === UInt.Lit(_a & _b))
+ assert((a | b) === UInt.Lit(_a | _b))
+ assert((a ^ b) === UInt.Lit(_a ^ _b))
stop()
}
diff --git a/src/test/scala/chiselTests/BundleWire.scala b/src/test/scala/chiselTests/BundleWire.scala
index 2f6322b1..3d3d58f3 100644
--- a/src/test/scala/chiselTests/BundleWire.scala
+++ b/src/test/scala/chiselTests/BundleWire.scala
@@ -7,8 +7,8 @@ import org.scalatest.prop._
import chisel3.testers.BasicTester
class Coord extends Bundle {
- val x = UInt(width = 32)
- val y = UInt(width = 32)
+ val x = UInt.width( 32)
+ val y = UInt.width( 32)
}
class BundleWire(n: Int) extends Module {
diff --git a/src/test/scala/chiselTests/ComplexAssign.scala b/src/test/scala/chiselTests/ComplexAssign.scala
index 638ef9b7..c5aaa554 100644
--- a/src/test/scala/chiselTests/ComplexAssign.scala
+++ b/src/test/scala/chiselTests/ComplexAssign.scala
@@ -17,11 +17,11 @@ class Complex[T <: Data](val re: T, val im: T) extends Bundle {
class ComplexAssign(w: Int) extends Module {
val io = IO(new Bundle {
val e = Input(Bool())
- val in = Input(new Complex(UInt(width = w), UInt(width = w)))
- val out = Output(new Complex(UInt(width = w), UInt(width = w)))
+ val in = Input(new Complex(UInt.width(w), UInt.width(w)))
+ val out = Output(new Complex(UInt.width(w), UInt.width(w)))
})
when (io.e) {
- val tmp = Wire(new Complex(UInt(width = w), UInt(width = w)))
+ val tmp = Wire(new Complex(UInt.width(w), UInt.width(w)))
tmp := io.in
io.out.re := tmp.re
io.out.im := tmp.im
diff --git a/src/test/scala/chiselTests/DeqIOSpec.scala b/src/test/scala/chiselTests/DeqIOSpec.scala
index 770d2e0e..cd8a5d63 100644
--- a/src/test/scala/chiselTests/DeqIOSpec.scala
+++ b/src/test/scala/chiselTests/DeqIOSpec.scala
@@ -12,7 +12,7 @@ import chisel3.util._
class UsesDeqIOInfo extends Bundle {
val test_width = 32
- val info_data = UInt(width = test_width)
+ val info_data = UInt.width(test_width)
}
class UsesDeqIO extends Module {
diff --git a/src/test/scala/chiselTests/GCD.scala b/src/test/scala/chiselTests/GCD.scala
index d0d945b7..5e4c897a 100644
--- a/src/test/scala/chiselTests/GCD.scala
+++ b/src/test/scala/chiselTests/GCD.scala
@@ -15,8 +15,8 @@ class GCD extends Module {
val z = Output(UInt.width(32))
val v = Output(Bool())
})
- val x = Reg(UInt(width = 32))
- val y = Reg(UInt(width = 32))
+ val x = Reg(UInt.width( 32))
+ val y = Reg(UInt.width( 32))
when (x > y) { x := x -% y }
.otherwise { y := y -% x }
when (io.e) { x := io.a; y := io.b }
diff --git a/src/test/scala/chiselTests/MultiAssign.scala b/src/test/scala/chiselTests/MultiAssign.scala
index 2399267e..fa4c4898 100644
--- a/src/test/scala/chiselTests/MultiAssign.scala
+++ b/src/test/scala/chiselTests/MultiAssign.scala
@@ -11,7 +11,7 @@ import chisel3.util._
class LastAssignTester() extends BasicTester {
val cnt = Counter(2)
- val test = Wire(UInt(width=4))
+ val test = Wire(UInt.width(4))
assert(test === 7.U) // allow read references before assign references
test := 13.U
diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala
index 5d4bd18d..8b9016b1 100644
--- a/src/test/scala/chiselTests/Reg.scala
+++ b/src/test/scala/chiselTests/Reg.scala
@@ -16,7 +16,7 @@ class RegSpec extends ChiselFlatSpec {
"A Reg" should "be of the same type and width as outType, if specified" in {
class RegOutTypeWidthTester extends BasicTester {
- val reg = Reg(t=UInt(width=2), next=Wire(UInt(width=3)), init=UInt.Lit(20))
+ val reg = Reg(t=UInt.width(2), next=Wire(UInt.width(3)), init=UInt.Lit(20))
reg.getWidth should be (2)
}
elaborate{ new RegOutTypeWidthTester }
@@ -24,11 +24,11 @@ class RegSpec extends ChiselFlatSpec {
"A Reg" should "be of unknown width if outType is not specified and width is not forced" in {
class RegUnknownWidthTester extends BasicTester {
- val reg1 = Reg(next=Wire(UInt(width=3)), init=20.U)
+ val reg1 = Reg(next=Wire(UInt.width(3)), init=20.U)
DataMirror.widthOf(reg1).known should be (false)
val reg2 = Reg(init=20.U)
DataMirror.widthOf(reg2).known should be (false)
- val reg3 = Reg(next=Wire(UInt(width=3)), init=5.U)
+ val reg3 = Reg(next=Wire(UInt.width(3)), init=5.U)
DataMirror.widthOf(reg3).known should be (false)
}
elaborate { new RegUnknownWidthTester }
diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala
index 156e5df2..665bb8e6 100644
--- a/src/test/scala/chiselTests/Risc.scala
+++ b/src/test/scala/chiselTests/Risc.scala
@@ -9,17 +9,17 @@ class Risc extends Module {
val io = IO(new Bundle {
val isWr = Input(Bool())
val wrAddr = Input(UInt.width(8))
- val wrData = Input(Bits(32))
+ val wrData = Input(Bits.width(32))
val boot = Input(Bool())
val valid = Output(Bool())
- val out = Output(Bits(32))
+ val out = Output(Bits.width(32))
})
val memSize = 256
- val file = Mem(memSize, Bits(width = 32))
- val code = Mem(memSize, Bits(width = 32))
+ val file = Mem(memSize, Bits.width(32))
+ val code = Mem(memSize, Bits.width(32))
val pc = Reg(init=UInt(0, 8))
- val add_op :: imm_op :: Nil = Enum(Bits(width = 8), 2)
+ val add_op :: imm_op :: Nil = Enum(Bits.width(8), 2)
val inst = code(pc)
val op = inst(31,24)
@@ -29,7 +29,7 @@ class Risc extends Module {
val ra = Mux(rai === 0.asUInt(), 0.asUInt(), file(rai))
val rb = Mux(rbi === 0.asUInt(), 0.asUInt(), file(rbi))
- val rc = Wire(Bits(width = 32))
+ val rc = Wire(Bits.width(32))
io.valid := Bool(false)
io.out := 0.asUInt()
diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala
index 440228c9..0c84e62a 100644
--- a/src/test/scala/chiselTests/Stack.scala
+++ b/src/test/scala/chiselTests/Stack.scala
@@ -16,7 +16,7 @@ class ChiselStack(val depth: Int) extends Module {
val dataOut = Output(UInt.width(32))
})
- val stack_mem = Mem(depth, UInt(width = 32))
+ val stack_mem = Mem(depth, UInt.width(32))
val sp = Reg(init = UInt(0, width = log2Up(depth + 1)))
val out = Reg(init = UInt(0, width = 32))
diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala
index 75c4278f..40730264 100644
--- a/src/test/scala/chiselTests/Tbl.scala
+++ b/src/test/scala/chiselTests/Tbl.scala
@@ -11,13 +11,13 @@ import chisel3.util._
class Tbl(w: Int, n: Int) extends Module {
val io = IO(new Bundle {
- val wi = Input(UInt(log2Up(n)))
- val ri = Input(UInt(log2Up(n)))
+ val wi = Input(UInt.width(log2Up(n)))
+ val ri = Input(UInt.width(log2Up(n)))
val we = Input(Bool())
val d = Input(UInt.width(w))
val o = Output(UInt.width(w))
})
- val m = Mem(n, UInt(width = w))
+ val m = Mem(n, UInt.width(w))
io.o := m(io.ri)
when (io.we) {
m(io.wi) := io.d
@@ -30,8 +30,8 @@ class Tbl(w: Int, n: Int) extends Module {
class TblTester(w: Int, n: Int, idxs: List[Int], values: List[Int]) extends BasicTester {
val (cnt, wrap) = Counter(Bool(true), idxs.size)
val dut = Module(new Tbl(w, n))
- val vvalues = Vec(values.map(UInt(_)))
- val vidxs = Vec(idxs.map(UInt(_)))
+ val vvalues = Vec(values.map(UInt.Lit(_)))
+ val vidxs = Vec(idxs.map(UInt.Lit(_)))
val prev_idx = vidxs(cnt - UInt.Lit(1))
val prev_value = vvalues(cnt - UInt.Lit(1))
dut.io.wi := vidxs(cnt)
diff --git a/src/test/scala/chiselTests/UIntOps.scala b/src/test/scala/chiselTests/UIntOps.scala
index 812f822d..69633461 100644
--- a/src/test/scala/chiselTests/UIntOps.scala
+++ b/src/test/scala/chiselTests/UIntOps.scala
@@ -86,7 +86,7 @@ class GoodBoolConversion extends Module {
class BadBoolConversion extends Module {
val io = IO(new Bundle {
- val u = Input(UInt(width = 5))
+ val u = Input(UInt.width( 5))
val b = Output(Bool())
})
io.b := io.u.toBool
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index cdb1ba8d..22b518a2 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -18,9 +18,9 @@ class ValueTester(w: Int, values: List[Int]) extends BasicTester {
}
class TabulateTester(n: Int) extends BasicTester {
- val v = Vec(Range(0, n).map(i => UInt(i * 2)))
- val x = Vec(Array.tabulate(n){ i => UInt(i * 2) })
- val u = Vec.tabulate(n)(i => UInt(i*2))
+ val v = Vec(Range(0, n).map(i => UInt.Lit(i * 2)))
+ val x = Vec(Array.tabulate(n){ i => UInt.Lit(i * 2) })
+ val u = Vec.tabulate(n)(i => UInt.Lit(i*2))
assert(v.toBits === x.toBits)
assert(v.toBits === u.toBits)
@@ -31,7 +31,7 @@ class TabulateTester(n: Int) extends BasicTester {
class ShiftRegisterTester(n: Int) extends BasicTester {
val (cnt, wrap) = Counter(Bool(true), n*2)
- val shifter = Reg(Vec(n, UInt(width = log2Up(n))))
+ val shifter = Reg(Vec(n, UInt.width(log2Up(n))))
(shifter, shifter drop 1).zipped.foreach(_ := _)
shifter(n-1) := cnt
when (cnt >= UInt.Lit(n)) {
diff --git a/src/test/scala/chiselTests/VectorPacketIO.scala b/src/test/scala/chiselTests/VectorPacketIO.scala
index 081990ad..6e1d267d 100644
--- a/src/test/scala/chiselTests/VectorPacketIO.scala
+++ b/src/test/scala/chiselTests/VectorPacketIO.scala
@@ -19,7 +19,7 @@ import chisel3.util._
* IMPORTANT: The canonical way to initialize a decoupled inteface is still being debated.
*/
class Packet extends Bundle {
- val header = UInt(width = 1)
+ val header = UInt.width(1)
}
/**
diff --git a/src/test/scala/chiselTests/When.scala b/src/test/scala/chiselTests/When.scala
index 58aa43e7..2f5c49e4 100644
--- a/src/test/scala/chiselTests/When.scala
+++ b/src/test/scala/chiselTests/When.scala
@@ -12,7 +12,7 @@ class WhenTester() extends BasicTester {
val cnt = Counter(4)
when(Bool(true)) { cnt.inc() }
- val out = Wire(UInt(width=3))
+ val out = Wire(UInt.width(3))
when(cnt.value === UInt.Lit(0)) {
out := UInt.Lit(1)
} .elsewhen (cnt.value === UInt.Lit(1)) {
@@ -34,7 +34,7 @@ class OverlappedWhenTester() extends BasicTester {
val cnt = Counter(4)
when(Bool(true)) { cnt.inc() }
- val out = Wire(UInt(width=3))
+ val out = Wire(UInt.width(3))
when(cnt.value <= UInt.Lit(0)) {
out := UInt.Lit(1)
} .elsewhen (cnt.value <= UInt.Lit(1)) {
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-31 21:31:02 +0000