3 files changed, 12 insertions, 9 deletions
diff --git a/src/test/scala/chiselTests/LFSR16.scala b/src/test/scala/chiselTests/LFSR16.scala
index 992bb4bf..d0f06865 100644
--- a/src/test/scala/chiselTests/LFSR16.scala
+++ b/src/test/scala/chiselTests/LFSR16.scala
@@ -51,10 +51,15 @@ class LFSRMaxPeriod(gen: => UInt) extends BasicTester {
   val seed = withReset(!started) { RegInit(rv) }
 
   val (_, wrap) = Counter(started, math.pow(2.0, rv.getWidth).toInt - 1)
+
   when (rv === seed && started) {
     chisel3.assert(wrap)
     stop()
   }
+
+  val last = RegNext(rv)
+  chisel3.assert(rv =/= last, "LFSR last value (0b%b) was equal to current value (0b%b)", rv, last)
+
 }
 
 /** Check that the output of the new LFSR is the same asthe old LFSR */
diff --git a/src/test/scala/chiselTests/util/random/LFSRSpec.scala b/src/test/scala/chiselTests/util/random/LFSRSpec.scala
index 5aedca75..ce0abf69 100644
--- a/src/test/scala/chiselTests/util/random/LFSRSpec.scala
+++ b/src/test/scala/chiselTests/util/random/LFSRSpec.scala
@@ -12,7 +12,7 @@ import chiselTests.{ChiselFlatSpec, LFSRDistribution, LFSRMaxPeriod}
 import math.pow
 
 class FooLFSR(val reduction: LFSRReduce, seed: Option[BigInt]) extends PRNG(4, seed) with LFSR {
-  def delta(s: UInt): UInt = s
+  def delta(s: Seq[Bool]): Seq[Bool] = s
 }
 
 /** This tests that after reset an LFSR is not locked up. This manually sets the seed of the LFSR at run-time to the
@@ -30,20 +30,18 @@ class LFSRResetTester(gen: => LFSR, lockUpValue: BigInt) extends BasicTester {
 
   val (count, done) = Counter(true.B, 5)
 
-  printf("%d: 0b%b\n", count, lfsr.io.out)
-
   lfsr.io.seed.valid := count === 1.U
-  lfsr.io.seed.bits := lockUpValue.U
+  lfsr.io.seed.bits := lockUpValue.U(lfsr.width.W).asBools
   lfsr.io.increment := true.B
 
   when (count === 2.U) {
-    assert(lfsr.io.out === lockUpValue.U, "LFSR is NOT locked up, but should be!")
+    assert(lfsr.io.out.asUInt === lockUpValue.U, "LFSR is NOT locked up, but should be!")
   }
 
   lfsr.reset := count === 3.U
 
   when (count === 4.U) {
-    assert(lfsr.io.out =/= lockUpValue.U, "LFSR is locked up, but should not be after reset!")
+    assert(lfsr.io.out.asUInt =/= lockUpValue.U, "LFSR is locked up, but should not be after reset!")
   }
 
   when (done) {
diff --git a/src/test/scala/chiselTests/util/random/PRNGSpec.scala b/src/test/scala/chiselTests/util/random/PRNGSpec.scala
index 138a6ceb..341fb685 100644
--- a/src/test/scala/chiselTests/util/random/PRNGSpec.scala
+++ b/src/test/scala/chiselTests/util/random/PRNGSpec.scala
@@ -12,7 +12,7 @@ import chiselTests.ChiselFlatSpec
 class CyclePRNG(width: Int, seed: Option[BigInt], step: Int, updateSeed: Boolean)
     extends PRNG(width, seed, step, updateSeed) {
 
-  def delta(s: UInt): UInt = s ## s(width - 1)
+  def delta(s: Seq[Bool]): Seq[Bool] = s.last +: s.dropRight(1)
 
 }
 
@@ -49,10 +49,10 @@ class PRNGUpdateSeedTest(updateSeed: Boolean, seed: BigInt, expected: BigInt) ex
 
   a.io.increment := true.B
   a.io.seed.valid := count === 2.U
-  a.io.seed.bits := seed.U
+  a.io.seed.bits := seed.U(a.width.W).asBools
 
   when (count === 3.U) {
-    assert(a.io.out === expected.U, "Output didn't match!")
+    assert(a.io.out.asUInt === expected.U, "Output didn't match!")
   }
 
   when (done) {