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Diffstat (limited to 'src/test/scala/chiselTests')
| -rw-r--r-- | src/test/scala/chiselTests/TesterDriverSpec.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/TesterDriverSpec.scala b/src/test/scala/chiselTests/TesterDriverSpec.scala index dfdd07cc..3c57daae 100644 --- a/src/test/scala/chiselTests/TesterDriverSpec.scala +++ b/src/test/scala/chiselTests/TesterDriverSpec.scala @@ -22,7 +22,7 @@ class FinishTester extends BasicTester { val test_wire = Wire(UInt(1, width = test_wire_width)) // though we just set test_wire to 1, the assert below will pass because - // the finish will change it's value + // the finish will change its value assert(test_wire === UInt(test_wire_override_value)) /** In finish we use last connect semantics to alter the test_wire in the circuit |