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Diffstat (limited to 'src/test/scala/chiselTests')
| -rw-r--r-- | src/test/scala/chiselTests/stage/ChiselStageSpec.scala | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/stage/ChiselStageSpec.scala b/src/test/scala/chiselTests/stage/ChiselStageSpec.scala index 167e414b..7b6a2d39 100644 --- a/src/test/scala/chiselTests/stage/ChiselStageSpec.scala +++ b/src/test/scala/chiselTests/stage/ChiselStageSpec.scala @@ -88,6 +88,13 @@ class ChiselStageSpec extends AnyFlatSpec with Matchers with Utils { catchWrites { ChiselStage.convert(new Foo) } shouldBe a[Right[_, _]] } + ignore should "generate a FIRRTL circuit from a CHIRRTL circuit" in { + info("no files were written") + catchWrites { + ChiselStage.convert(ChiselStage.elaborate(new Foo)) + } shouldBe a[Right[_, _]] + } + behavior of "ChiselStage$.emitChirrtl" ignore should "generate a CHIRRTL string from a Chisel module" in { |