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Diffstat (limited to 'src/test/scala/chiselTests')
| -rw-r--r-- | src/test/scala/chiselTests/PrintableSpec.scala | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/src/test/scala/chiselTests/PrintableSpec.scala b/src/test/scala/chiselTests/PrintableSpec.scala index d733ab8c..c6ba0a1d 100644 --- a/src/test/scala/chiselTests/PrintableSpec.scala +++ b/src/test/scala/chiselTests/PrintableSpec.scala @@ -8,10 +8,8 @@ import chisel3.testers.BasicTester /* Printable Tests */ class PrintableSpec extends FlatSpec with Matchers { - private val PrintfRegex = """\s*printf\((.*)\).*""".r - // This regex is brittle, it relies on the first two arguments of the printf - // not containing quotes, problematic if Chisel were to emit UInt<1>("h01") - // instead of the current UInt<1>(1) for the enable signal + // This regex is brittle, it specifically finds the clock and enable signals followed by commas + private val PrintfRegex = """\s*printf\(\w+, [^,]+,(.*)\).*""".r private val StringRegex = """([^"]*)"(.*?)"(.*)""".r private case class Printf(str: String, args: Seq[String]) private def getPrintfs(firrtl: String): Seq[Printf] = { |