diff options
Diffstat (limited to 'src/test/scala/chiselTests/util')
7 files changed, 152 insertions, 130 deletions
diff --git a/src/test/scala/chiselTests/util/BitPatSpec.scala b/src/test/scala/chiselTests/util/BitPatSpec.scala index 549e8bca..38ffc3ba 100644 --- a/src/test/scala/chiselTests/util/BitPatSpec.scala +++ b/src/test/scala/chiselTests/util/BitPatSpec.scala @@ -6,13 +6,12 @@ import chisel3.util.BitPat import org.scalatest.flatspec.AnyFlatSpec import org.scalatest.matchers.should.Matchers - class BitPatSpec extends AnyFlatSpec with Matchers { - behavior of classOf[BitPat].toString + behavior.of(classOf[BitPat].toString) it should "convert a BitPat to readable form" in { val testPattern = "0" * 32 + "1" * 32 + "?" * 32 + "?01" * 32 - BitPat("b" + testPattern).toString should be (s"BitPat($testPattern)") + BitPat("b" + testPattern).toString should be(s"BitPat($testPattern)") } it should "convert a BitPat to raw form" in { @@ -21,15 +20,15 @@ class BitPatSpec extends AnyFlatSpec with Matchers { } it should "not fail if BitPat width is 0" in { - intercept[IllegalArgumentException]{BitPat("b")} + intercept[IllegalArgumentException] { BitPat("b") } } it should "concat BitPat via ##" in { - (BitPat.Y(4) ## BitPat.dontCare(3) ## BitPat.N(2)).toString should be (s"BitPat(1111???00)") + (BitPat.Y(4) ## BitPat.dontCare(3) ## BitPat.N(2)).toString should be(s"BitPat(1111???00)") } it should "throw when BitPat apply to a Hardware" in { - intercept[java.lang.IllegalArgumentException]{ + intercept[java.lang.IllegalArgumentException] { chisel3.stage.ChiselStage.emitChirrtl(new chisel3.Module { BitPat(chisel3.Reg(chisel3.Bool())) }) diff --git a/src/test/scala/chiselTests/util/BitSetSpec.scala b/src/test/scala/chiselTests/util/BitSetSpec.scala index 8120cc97..dd66ba40 100644 --- a/src/test/scala/chiselTests/util/BitSetSpec.scala +++ b/src/test/scala/chiselTests/util/BitSetSpec.scala @@ -6,14 +6,13 @@ import org.scalatest.flatspec.AnyFlatSpec import org.scalatest.matchers.should.Matchers class BitSetSpec extends AnyFlatSpec with Matchers { - behavior of classOf[BitSet].toString + behavior.of(classOf[BitSet].toString) it should "reject unequal width when constructing a BitSet" in { intercept[IllegalArgumentException] { - BitSet.fromString( - """b0010 - |b00010 - |""".stripMargin) + BitSet.fromString("""b0010 + |b00010 + |""".stripMargin) } } @@ -21,7 +20,7 @@ class BitSetSpec extends AnyFlatSpec with Matchers { val aBitPat = BitPat("b10?") val bBitPat = BitPat("b1??") - aBitPat.subtract(bBitPat).isEmpty should be (true) + aBitPat.subtract(bBitPat).isEmpty should be(true) } it should "return nonempty subtraction result correctly" in { @@ -31,20 +30,19 @@ class BitSetSpec extends AnyFlatSpec with Matchers { val dBitPat = BitPat("b100") val diffBitPat = bBitPat.subtract(aBitPat) - bBitPat.cover(diffBitPat) should be (true) - diffBitPat.equals(cBitPat) should be (true) + bBitPat.cover(diffBitPat) should be(true) + diffBitPat.equals(cBitPat) should be(true) val largerdiffBitPat = bBitPat.subtract(dBitPat) - aBitPat.cover(dBitPat) should be (true) - largerdiffBitPat.cover(diffBitPat) should be (true) + aBitPat.cover(dBitPat) should be(true) + largerdiffBitPat.cover(diffBitPat) should be(true) } it should "be able to handle complex subtract between BitSet" in { - val aBitSet = BitSet.fromString( - """b?01?0 - |b11111 - |b00000 - |""".stripMargin) + val aBitSet = BitSet.fromString("""b?01?0 + |b11111 + |b00000 + |""".stripMargin) val bBitSet = BitSet.fromString( """b?1111 |b?0000 @@ -52,44 +50,41 @@ class BitSetSpec extends AnyFlatSpec with Matchers { ) val expected = BitPat("b?01?0") - expected.equals(aBitSet.subtract(bBitSet)) should be (true) + expected.equals(aBitSet.subtract(bBitSet)) should be(true) } it should "be generated from BitPat union" in { - val aBitSet = BitSet.fromString( - """b001?0 - |b000??""".stripMargin) + val aBitSet = BitSet.fromString("""b001?0 + |b000??""".stripMargin) val aBitPat = BitPat("b000??") val bBitPat = BitPat("b001?0") val cBitPat = BitPat("b00000") - aBitPat.cover(cBitPat) should be (true) - aBitSet.cover(bBitPat) should be (true) + aBitPat.cover(cBitPat) should be(true) + aBitSet.cover(bBitPat) should be(true) - aBitSet.equals(aBitPat.union(bBitPat)) should be (true) + aBitSet.equals(aBitPat.union(bBitPat)) should be(true) } it should "be generated from BitPat subtraction" in { - val aBitSet = BitSet.fromString( - """b001?0 - |b000??""".stripMargin) + val aBitSet = BitSet.fromString("""b001?0 + |b000??""".stripMargin) val aBitPat = BitPat("b00???") val bBitPat = BitPat("b001?1") - aBitSet.equals(aBitPat.subtract(bBitPat)) should be (true) + aBitSet.equals(aBitPat.subtract(bBitPat)) should be(true) } it should "union two BitSet together" in { - val aBitSet = BitSet.fromString( - """b001?0 - |b001?1 - |""".stripMargin) + val aBitSet = BitSet.fromString("""b001?0 + |b001?1 + |""".stripMargin) val bBitSet = BitSet.fromString( """b000?? |b01??? |""".stripMargin ) val cBitPat = BitPat("b0????") - cBitPat.equals(aBitSet.union(bBitSet)) should be (true) + cBitPat.equals(aBitSet.union(bBitSet)) should be(true) } it should "be decoded" in { @@ -100,19 +95,23 @@ class BitSetSpec extends AnyFlatSpec with Matchers { chisel3.stage.ChiselStage.emitSystemVerilog(new Module { val in = IO(Input(UInt(8.W))) val out = IO(Output(UInt(4.W))) - out := decoder.bitset(in, Seq( - BitSet.fromString( - "b000?????" + out := decoder.bitset( + in, + Seq( + BitSet.fromString( + "b000?????" + ), + BitSet.fromString( + """b0010???? + |b01?????? + |""".stripMargin + ), + BitSet.fromString( + "b11??????" + ) ), - BitSet.fromString( - """b0010???? - |b01?????? - |""".stripMargin - ), - BitSet.fromString( - "b11??????" - ) - ), true) + true + ) }) } diff --git a/src/test/scala/chiselTests/util/CatSpec.scala b/src/test/scala/chiselTests/util/CatSpec.scala index 79d2c027..a75c4ec0 100644 --- a/src/test/scala/chiselTests/util/CatSpec.scala +++ b/src/test/scala/chiselTests/util/CatSpec.scala @@ -12,7 +12,7 @@ import chiselTests.ChiselFlatSpec object CatSpec { class JackIsATypeSystemGod extends Module { - val in = IO(Input (Vec(0, UInt(8.W)))) + val in = IO(Input(Vec(0, UInt(8.W)))) val out = IO(Output(UInt(8.W))) out := Cat(in) @@ -24,7 +24,7 @@ class CatSpec extends ChiselFlatSpec { import CatSpec._ - behavior of "util.Cat" + behavior.of("util.Cat") it should "not fail to elaborate a zero-element Vec" in { @@ -41,7 +41,7 @@ class CatSpec extends ChiselFlatSpec { } val chirrtl = ChiselStage.emitChirrtl(new MyModule) for (name <- Seq("a", "b", "c", "d")) { - chirrtl should include (s"input $name : UInt<8>") + chirrtl should include(s"input $name : UInt<8>") } } @@ -54,11 +54,10 @@ class CatSpec extends ChiselFlatSpec { out := noPrefix(Cat(in)) } val chirrtl = ChiselStage.emitChirrtl(new MyModule) - chirrtl should include ("node lo_lo = cat(in[6], in[7])") - chirrtl should include ("node lo_hi = cat(in[4], in[5])") - chirrtl should include ("node hi_lo = cat(in[2], in[3])") - chirrtl should include ("node hi_hi = cat(in[0], in[1])") + chirrtl should include("node lo_lo = cat(in[6], in[7])") + chirrtl should include("node lo_hi = cat(in[4], in[5])") + chirrtl should include("node hi_lo = cat(in[2], in[3])") + chirrtl should include("node hi_hi = cat(in[0], in[1])") } - } diff --git a/src/test/scala/chiselTests/util/experimental/PlaSpec.scala b/src/test/scala/chiselTests/util/experimental/PlaSpec.scala index 8af5c936..156249a2 100644 --- a/src/test/scala/chiselTests/util/experimental/PlaSpec.scala +++ b/src/test/scala/chiselTests/util/experimental/PlaSpec.scala @@ -3,7 +3,7 @@ package chiselTests.util.experimental import chisel3._ import chisel3.stage.PrintFullStackTraceAnnotation import chisel3.testers.BasicTester -import chisel3.util.{BitPat, pla} +import chisel3.util.{pla, BitPat} import chiselTests.ChiselFlatSpec class PlaSpec extends ChiselFlatSpec { @@ -17,12 +17,17 @@ class PlaSpec extends ChiselFlatSpec { (BitPat("b100"), BitPat("b00010000")), (BitPat("b101"), BitPat("b00100000")), (BitPat("b110"), BitPat("b01000000")), - (BitPat("b111"), BitPat("b10000000")), + (BitPat("b111"), BitPat("b10000000")) ) - table.foreach { case (i, o) => - val (plaIn, plaOut) = pla(table) - plaIn := WireDefault(i.value.U(3.W)) - chisel3.assert(plaOut === o.value.U(8.W), "Input " + i.toString + " produced incorrect output BitPat(%b)", plaOut) + table.foreach { + case (i, o) => + val (plaIn, plaOut) = pla(table) + plaIn := WireDefault(i.value.U(3.W)) + chisel3.assert( + plaOut === o.value.U(8.W), + "Input " + i.toString + " produced incorrect output BitPat(%b)", + plaOut + ) } stop() }) @@ -38,12 +43,17 @@ class PlaSpec extends ChiselFlatSpec { (BitPat("b100"), BitPat("b00010000")), (BitPat("b101"), BitPat("b00100000")), (BitPat("b110"), BitPat("b01000000")), - (BitPat("b111"), BitPat("b10000000")), + (BitPat("b111"), BitPat("b10000000")) ) - table.foreach { case (i, o) => - val (plaIn, plaOut) = pla(table, BitPat("b11111111")) - plaIn := WireDefault(i.value.U(3.W)) - chisel3.assert(plaOut === ~o.value.U(8.W), "Input " + i.toString + " produced incorrect output BitPat(%b)", plaOut) + table.foreach { + case (i, o) => + val (plaIn, plaOut) = pla(table, BitPat("b11111111")) + plaIn := WireDefault(i.value.U(3.W)) + chisel3.assert( + plaOut === ~o.value.U(8.W), + "Input " + i.toString + " produced incorrect output BitPat(%b)", + plaOut + ) } stop() }) @@ -53,12 +63,13 @@ class PlaSpec extends ChiselFlatSpec { assertTesterPasses(new BasicTester { val table = Seq( (BitPat("b000"), BitPat("b?01")), - (BitPat("b111"), BitPat("b?01")), + (BitPat("b111"), BitPat("b?01")) ) - table.foreach { case (i, o) => - val (plaIn, plaOut) = pla(table) - plaIn := WireDefault(i.value.U(3.W)) - chisel3.assert(o === plaOut, "Input " + i.toString + " produced incorrect output BitPat(%b)", plaOut) + table.foreach { + case (i, o) => + val (plaIn, plaOut) = pla(table) + plaIn := WireDefault(i.value.U(3.W)) + chisel3.assert(o === plaOut, "Input " + i.toString + " produced incorrect output BitPat(%b)", plaOut) } stop() }) @@ -82,12 +93,17 @@ class PlaSpec extends ChiselFlatSpec { (BitPat("b1100"), BitPat("b0")), (BitPat("b1101"), BitPat("b1")), (BitPat("b1110"), BitPat("b1")), - (BitPat("b1111"), BitPat("b1")), + (BitPat("b1111"), BitPat("b1")) ) - table.foreach { case (i, o) => - val (plaIn, plaOut) = pla(table) - plaIn := WireDefault(i.value.U(4.W)) - chisel3.assert(plaOut === o.value.U(1.W), "Input " + i.toString + " produced incorrect output BitPat(%b)", plaOut) + table.foreach { + case (i, o) => + val (plaIn, plaOut) = pla(table) + plaIn := WireDefault(i.value.U(4.W)) + chisel3.assert( + plaOut === o.value.U(1.W), + "Input " + i.toString + " produced incorrect output BitPat(%b)", + plaOut + ) } stop() }) diff --git a/src/test/scala/chiselTests/util/experimental/TruthTableSpec.scala b/src/test/scala/chiselTests/util/experimental/TruthTableSpec.scala index 255effaf..2ef316bb 100644 --- a/src/test/scala/chiselTests/util/experimental/TruthTableSpec.scala +++ b/src/test/scala/chiselTests/util/experimental/TruthTableSpec.scala @@ -4,7 +4,7 @@ package chiselTests.util.experimental import chisel3._ import chisel3.util.BitPat -import chisel3.util.experimental.decode.{TruthTable, decoder} +import chisel3.util.experimental.decode.{decoder, TruthTable} import org.scalatest.flatspec.AnyFlatSpec class TruthTableSpec extends AnyFlatSpec { @@ -64,15 +64,14 @@ class TruthTableSpec extends AnyFlatSpec { "TruthTable" should "be reproducible" in { class Foo extends Module { - val io = IO(new Bundle{ + val io = IO(new Bundle { val in = Input(UInt(4.W)) val out = Output(UInt(16.W)) }) - val table = TruthTable( - (0 until 16).map{ - i => BitPat(i.U(4.W)) -> BitPat((1<<i).U(16.W)) + (0 until 16).map { i => + BitPat(i.U(4.W)) -> BitPat((1 << i).U(16.W)) }, BitPat.dontCare(16) ) diff --git a/src/test/scala/chiselTests/util/random/LFSRSpec.scala b/src/test/scala/chiselTests/util/random/LFSRSpec.scala index 975a3c93..d47c2d7d 100644 --- a/src/test/scala/chiselTests/util/random/LFSRSpec.scala +++ b/src/test/scala/chiselTests/util/random/LFSRSpec.scala @@ -23,7 +23,7 @@ class LFSRMaxPeriod(gen: => UInt) extends BasicTester { val (_, wrap) = Counter(started, math.pow(2.0, rv.getWidth).toInt - 1) - when (rv === seed && started) { + when(rv === seed && started) { chisel3.assert(wrap) stop() } @@ -49,7 +49,7 @@ class LFSRDistribution(gen: => UInt, cycles: Int = 10000) extends BasicTester { val (trial, done) = Counter(true.B, cycles) - val rollValue = die0 +& die1 // Note +& is critical because sum will need an extra bit. + val rollValue = die0 +& die1 // Note +& is critical because sum will need an extra bit. bins(rollValue) := bins(rollValue) + 1.U @@ -88,17 +88,17 @@ class LFSRResetTester(gen: => LFSR, lockUpValue: BigInt) extends BasicTester { lfsr.io.seed.bits := lockUpValue.U(lfsr.width.W).asBools lfsr.io.increment := true.B - when (count === 2.U) { + when(count === 2.U) { assert(lfsr.io.out.asUInt === lockUpValue.U, "LFSR is NOT locked up, but should be!") } lfsr.reset := count === 3.U - when (count === 4.U) { + when(count === 4.U) { assert(lfsr.io.out.asUInt =/= lockUpValue.U, "LFSR is locked up, but should not be after reset!") } - when (done) { + when(done) { stop() } @@ -110,29 +110,34 @@ class LFSRSpec extends ChiselFlatSpec with Utils { val testName = s"have a maximal period over a range of widths (${range.head} to ${range.last})" + s" using ${reduction.getClass}" it should testName in { - range - .foreach{ width => - LFSR.tapsMaxPeriod(width).foreach{ taps => - info(s"""width $width okay using taps: ${taps.mkString(", ")}""") - assertTesterPasses(new LFSRMaxPeriod(PRNG(gen(width, taps, reduction))), - annotations = TesterDriver.verilatorOnly) - } + range.foreach { width => + LFSR.tapsMaxPeriod(width).foreach { taps => + info(s"""width $width okay using taps: ${taps.mkString(", ")}""") + assertTesterPasses( + new LFSRMaxPeriod(PRNG(gen(width, taps, reduction))), + annotations = TesterDriver.verilatorOnly + ) } + } } } - behavior of "LFSR" + behavior.of("LFSR") it should "throw an exception if initialized to a seed of zero for XOR configuration" in { - { the [IllegalArgumentException] thrownBy extractCause[IllegalArgumentException] { - ChiselStage.elaborate(new FooLFSR(XOR, Some(0))) } - }.getMessage should include ("Seed cannot be zero") + { + the[IllegalArgumentException] thrownBy extractCause[IllegalArgumentException] { + ChiselStage.elaborate(new FooLFSR(XOR, Some(0))) + } + }.getMessage should include("Seed cannot be zero") } it should "throw an exception if initialized to a seed of all ones for XNOR configuration" in { - { the [IllegalArgumentException] thrownBy extractCause[IllegalArgumentException] { - ChiselStage.elaborate(new FooLFSR(XNOR, Some(15))) } - }.getMessage should include ("Seed cannot be all ones") + { + the[IllegalArgumentException] thrownBy extractCause[IllegalArgumentException] { + ChiselStage.elaborate(new FooLFSR(XNOR, Some(15))) + } + }.getMessage should include("Seed cannot be all ones") } it should "reset correctly without a seed for XOR configuration" in { @@ -143,34 +148,35 @@ class LFSRSpec extends ChiselFlatSpec with Utils { assertTesterPasses(new LFSRResetTester(new FooLFSR(XNOR, None), 15)) } - behavior of "MaximalPeriodGaloisLFSR" + behavior.of("MaximalPeriodGaloisLFSR") it should "throw an exception if no LFSR taps are known" in { - { the [IllegalArgumentException] thrownBy extractCause[IllegalArgumentException] { - ChiselStage.elaborate(new MaxPeriodGaloisLFSR(787)) } - }.getMessage should include ("No max period LFSR taps stored for requested width") + { + the[IllegalArgumentException] thrownBy extractCause[IllegalArgumentException] { + ChiselStage.elaborate(new MaxPeriodGaloisLFSR(787)) + } + }.getMessage should include("No max period LFSR taps stored for requested width") } - periodCheck((w: Int, t: Set[Int], r: LFSRReduce) => new GaloisLFSR(w, t, reduction=r), XOR, 2 to 16) - periodCheck((w: Int, t: Set[Int], r: LFSRReduce) => new GaloisLFSR(w, t, reduction=r), XNOR, 2 to 16) + periodCheck((w: Int, t: Set[Int], r: LFSRReduce) => new GaloisLFSR(w, t, reduction = r), XOR, 2 to 16) + periodCheck((w: Int, t: Set[Int], r: LFSRReduce) => new GaloisLFSR(w, t, reduction = r), XNOR, 2 to 16) ignore should "have a sane distribution for larger widths" in { - ((17 to 32) ++ Seq(64, 128, 256, 512, 1024, 2048, 4096)) - .foreach{ width => - info(s"width $width okay!") - assertTesterPasses(new LFSRDistribution(LFSR(width), math.pow(2, 22).toInt)) - } + ((17 to 32) ++ Seq(64, 128, 256, 512, 1024, 2048, 4096)).foreach { width => + info(s"width $width okay!") + assertTesterPasses(new LFSRDistribution(LFSR(width), math.pow(2, 22).toInt)) + } } - behavior of "MaximalPeriodFibonacciLFSR" + behavior.of("MaximalPeriodFibonacciLFSR") - periodCheck((w: Int, t: Set[Int], r: LFSRReduce) => new FibonacciLFSR(w, t, reduction=r), XOR, 2 to 16) - periodCheck((w: Int, t: Set[Int], r: LFSRReduce) => new FibonacciLFSR(w, t, reduction=r), XNOR, 2 to 16) + periodCheck((w: Int, t: Set[Int], r: LFSRReduce) => new FibonacciLFSR(w, t, reduction = r), XOR, 2 to 16) + periodCheck((w: Int, t: Set[Int], r: LFSRReduce) => new FibonacciLFSR(w, t, reduction = r), XNOR, 2 to 16) - behavior of "LFSR maximal period taps" + behavior.of("LFSR maximal period taps") it should "contain all the expected widths" in { - ((2 to 786) ++ Seq(1024, 2048, 4096)).foreach(LFSR.tapsMaxPeriod.keys should contain (_)) + ((2 to 786) ++ Seq(1024, 2048, 4096)).foreach(LFSR.tapsMaxPeriod.keys should contain(_)) } } diff --git a/src/test/scala/chiselTests/util/random/PRNGSpec.scala b/src/test/scala/chiselTests/util/random/PRNGSpec.scala index 71a8635c..36fdf9cb 100644 --- a/src/test/scala/chiselTests/util/random/PRNGSpec.scala +++ b/src/test/scala/chiselTests/util/random/PRNGSpec.scala @@ -28,15 +28,15 @@ class PRNGStepTest extends BasicTester { val (_, done) = Counter(true.B, 16) - when (count2 === 0.U) { + when(count2 === 0.U) { assert(a === b, "1-step and 2-step PRNGs did not agree! (0b%b != 0b%b)", a, b) } - when (count4 === 0.U) { + when(count4 === 0.U) { assert(a === c, "1-step and 4-step PRNGs did not agree!") } - when (done) { + when(done) { stop() } @@ -52,11 +52,11 @@ class PRNGUpdateSeedTest(updateSeed: Boolean, seed: BigInt, expected: BigInt) ex a.io.seed.valid := count === 2.U a.io.seed.bits := seed.U(a.width.W).asBools - when (count === 3.U) { + when(count === 3.U) { assert(a.io.out.asUInt === expected.U, "Output didn't match!") } - when (done) { + when(done) { stop() } @@ -64,18 +64,22 @@ class PRNGUpdateSeedTest(updateSeed: Boolean, seed: BigInt, expected: BigInt) ex class PRNGSpec extends ChiselFlatSpec with Utils { - behavior of "PRNG" + behavior.of("PRNG") it should "throw an exception if the step size is < 1" in { - { the [IllegalArgumentException] thrownBy extractCause[IllegalArgumentException] { - ChiselStage.elaborate(new CyclePRNG(0, Some(1), 1, true)) } - }.getMessage should include ("Width must be greater than zero!") + { + the[IllegalArgumentException] thrownBy extractCause[IllegalArgumentException] { + ChiselStage.elaborate(new CyclePRNG(0, Some(1), 1, true)) + } + }.getMessage should include("Width must be greater than zero!") } it should "throw an exception if the step size is <= 0" in { - { the [IllegalArgumentException] thrownBy extractCause[IllegalArgumentException] { - ChiselStage.elaborate(new CyclePRNG(1, Some(1), 0, true)) } - }.getMessage should include ("Step size must be greater than one!") + { + the[IllegalArgumentException] thrownBy extractCause[IllegalArgumentException] { + ChiselStage.elaborate(new CyclePRNG(1, Some(1), 0, true)) + } + }.getMessage should include("Step size must be greater than one!") } it should "handle non-unary steps" in { |