diff options
Diffstat (limited to 'src/test/scala/chiselTests/experimental')
6 files changed, 174 insertions, 3 deletions
diff --git a/src/test/scala/chiselTests/experimental/DataMirrorSpec.scala b/src/test/scala/chiselTests/experimental/DataMirrorSpec.scala index 731596ec..09fdf3c4 100644 --- a/src/test/scala/chiselTests/experimental/DataMirrorSpec.scala +++ b/src/test/scala/chiselTests/experimental/DataMirrorSpec.scala @@ -8,7 +8,26 @@ import chisel3.stage.ChiselStage import chisel3.experimental.DataMirror import chiselTests.ChiselFlatSpec +object DataMirrorSpec { + import org.scalatest.matchers.should.Matchers._ + class GrandChild(parent: RawModule) extends Module { + DataMirror.getParent(this) should be(Some(parent)) + } + class Child(parent: RawModule) extends Module { + val inst = Module(new GrandChild(this)) + DataMirror.getParent(inst) should be(Some(this)) + DataMirror.getParent(this) should be(Some(parent)) + } + class Parent extends Module { + val inst = Module(new Child(this)) + DataMirror.getParent(inst) should be(Some(this)) + DataMirror.getParent(this) should be(None) + } +} + class DataMirrorSpec extends ChiselFlatSpec { + import DataMirrorSpec._ + behavior.of("DataMirror") def assertBinding(x: Data, io: Boolean, wire: Boolean, reg: Boolean) = { @@ -55,4 +74,18 @@ class DataMirrorSpec extends ChiselFlatSpec { } ChiselStage.elaborate(new MyModule) } + + it should "support getParent for normal modules" in { + ChiselStage.elaborate(new Parent) + } + + it should "support getParent for normal modules even when used in a D/I context" in { + import chisel3.experimental.hierarchy._ + class Top extends Module { + val defn = Definition(new Parent) + val inst = Instance(defn) + DataMirror.getParent(this) should be(None) + } + ChiselStage.elaborate(new Top) + } } diff --git a/src/test/scala/chiselTests/experimental/DataView.scala b/src/test/scala/chiselTests/experimental/DataView.scala index ac8357f0..cefc893c 100644 --- a/src/test/scala/chiselTests/experimental/DataView.scala +++ b/src/test/scala/chiselTests/experimental/DataView.scala @@ -7,7 +7,7 @@ import chisel3._ import chisel3.experimental.dataview._ import chisel3.experimental.conversions._ import chisel3.experimental.DataMirror.internal.chiselTypeClone -import chisel3.experimental.HWTuple2 +import chisel3.experimental.{Analog, HWTuple2} import chisel3.stage.ChiselStage import chisel3.util.{Decoupled, DecoupledIO} @@ -91,6 +91,16 @@ class DataViewSpec extends ChiselFlatSpec { chirrtl should include("bar <= in") } + it should "handle viewing Analogs as Analogs" in { + class MyModule extends Module { + val foo = IO(Analog(8.W)) + val bar = IO(Analog(8.W)) + foo <> bar.viewAs[Analog] + } + val chirrtl = ChiselStage.emitChirrtl(new MyModule) + chirrtl should include("attach (foo, bar)") + } + it should "handle viewing Bundles as their same concrete type" in { class MyBundle extends Bundle { val foo = UInt(8.W) @@ -177,6 +187,28 @@ class DataViewSpec extends ChiselFlatSpec { chirrtl should include("fooOut.foo <= barIn.foo") } + it should "be easy to make a PartialDataView viewing a Bundle as a Parent Bundle type" in { + class Foo(x: Int) extends Bundle { + val foo = UInt(x.W) + } + class Bar(val x: Int) extends Foo(x) { + val bar = UInt(x.W) + } + implicit val view = PartialDataView.supertype[Bar, Foo](b => new Foo(b.x)) + class MyModule extends Module { + val fooIn = IO(Input(new Foo(8))) + val barOut = IO(Output(new Bar(8))) + barOut.viewAs[Foo] := fooIn + + val barIn = IO(Input(new Bar(8))) + val fooOut = IO(Output(new Foo(8))) + fooOut := barIn.viewAs[Foo] + } + val chirrtl = ChiselStage.emitChirrtl(new MyModule) + chirrtl should include("barOut.foo <= fooIn.foo") + chirrtl should include("fooOut.foo <= barIn.foo") + } + it should "error if viewing a parent Bundle as a child Bundle type" in { assertTypeError(""" class Foo extends Bundle { diff --git a/src/test/scala/chiselTests/experimental/FlatIOSpec.scala b/src/test/scala/chiselTests/experimental/FlatIOSpec.scala index dfce447f..ebb7cbdb 100644 --- a/src/test/scala/chiselTests/experimental/FlatIOSpec.scala +++ b/src/test/scala/chiselTests/experimental/FlatIOSpec.scala @@ -5,7 +5,7 @@ package chiselTests.experimental import chisel3._ import chisel3.util.Valid import chisel3.stage.ChiselStage.emitChirrtl -import chisel3.experimental.FlatIO +import chisel3.experimental.{Analog, FlatIO} import chiselTests.ChiselFlatSpec class FlatIOSpec extends ChiselFlatSpec { @@ -48,4 +48,19 @@ class FlatIOSpec extends ChiselFlatSpec { val chirrtl = emitChirrtl(new MyModule) chirrtl should include("out[addr] <= in[addr]") } + + it should "support Analog members" in { + class MyBundle extends Bundle { + val foo = Output(UInt(8.W)) + val bar = Analog(8.W) + } + class MyModule extends RawModule { + val in = IO(Flipped(new MyBundle)) + val out = IO(new MyBundle) + out <> in + } + val chirrtl = emitChirrtl(new MyModule) + chirrtl should include("out.foo <= in.foo") + chirrtl should include("attach (out.bar, in.bar)") + } } diff --git a/src/test/scala/chiselTests/experimental/ForceNames.scala b/src/test/scala/chiselTests/experimental/ForceNames.scala index 233b4a5f..9ba825c4 100644 --- a/src/test/scala/chiselTests/experimental/ForceNames.scala +++ b/src/test/scala/chiselTests/experimental/ForceNames.scala @@ -59,7 +59,7 @@ object ForceNamesHierarchy { } } -class ForceNamesSpec extends ChiselFlatSpec { +class ForceNamesSpec extends ChiselFlatSpec with Utils { def run[T <: RawModule]( dut: => T, @@ -110,4 +110,19 @@ class ForceNamesSpec extends ChiselFlatSpec { ) } } + + "Force Name of non-hardware value" should "warn" in { + class Example extends Module { + val tpe = UInt(8.W) + forceName(tpe, "foobar") + + val in = IO(Input(tpe)) + val out = IO(Output(tpe)) + out := in + } + + val (log, foo) = grabLog(chisel3.stage.ChiselStage.elaborate(new Example)) + log should include("deprecated") + log should include("Using forceName 'foobar' on non-hardware value UInt<8>") + } } diff --git a/src/test/scala/chiselTests/experimental/hierarchy/Examples.scala b/src/test/scala/chiselTests/experimental/hierarchy/Examples.scala index fa26cbde..27725c49 100644 --- a/src/test/scala/chiselTests/experimental/hierarchy/Examples.scala +++ b/src/test/scala/chiselTests/experimental/hierarchy/Examples.scala @@ -271,4 +271,70 @@ object Examples { @public val mem = Mem(8, UInt(32.W)) @public val syncReadMem = SyncReadMem(8, UInt(32.W)) } + + @instantiable + class LeafInstantiable(val bundle: Data) { + @public val bundle = bundle + } + + @instantiable + class NestedInstantiable(val in: LeafInstantiable, val out: LeafInstantiable) { + @public val in = in + @public val out = out + } + + @instantiable + class AddOneNestedInstantiableData(width: Int) extends Module { + @public val in = IO(Input(UInt(width.W))) + @public val out = IO(Output(UInt(width.W))) + out := in + 1.U + + @public val leafOut = new LeafInstantiable(out) + @public val leafIn = new LeafInstantiable(in) + @public val nested = new NestedInstantiable(in = leafIn, out = leafOut) + + } + + class AddTwoNestedInstantiableData(width: Int) extends Module { + val in = IO(Input(UInt(width.W))) + val out = IO(Output(UInt(width.W))) + val addOneDef = Definition(new AddOneNestedInstantiableData(width)) + val i0 = Instance(addOneDef) + val i1 = Instance(addOneDef) + i0.in := in + i1.in := i0.out + out := i1.out + + // both are equivalent to the above + i1.leafIn.bundle := i0.leafOut.bundle + i1.nested.in.bundle := i0.nested.out.bundle + } + + class AddTwoNestedInstantiableDataSubmodule(addOneDef: Definition[AddOneNestedInstantiableData]) extends Module { + val in = IO(Input(UInt(addOneDef.in.getWidth.W))) + val out = IO(Output(UInt(addOneDef.out.getWidth.W))) + val i0 = Instance(addOneDef) + val i1 = Instance(addOneDef) + i0.in := in + i1.in := i0.out + out := i1.out + + // both are equivalent to the above + i1.leafIn.bundle := i0.leafOut.bundle + i1.nested.in.bundle := i0.nested.out.bundle + } + + class AddTwoNestedInstantiableDataWrapper(width: Int) extends Module { + val in = IO(Input(UInt(width.W))) + val out = IO(Output(UInt(width.W))) + + val original = Module(new AddOneNestedInstantiableData(width)) + val copy = Module(new AddTwoNestedInstantiableDataSubmodule(original.toDefinition)) + + original.in := in + copy.in := original.out + out := copy.out + + } + } diff --git a/src/test/scala/chiselTests/experimental/hierarchy/InstanceSpec.scala b/src/test/scala/chiselTests/experimental/hierarchy/InstanceSpec.scala index 8d8f7ea5..6596cd51 100644 --- a/src/test/scala/chiselTests/experimental/hierarchy/InstanceSpec.scala +++ b/src/test/scala/chiselTests/experimental/hierarchy/InstanceSpec.scala @@ -364,6 +364,16 @@ class InstanceSpec extends ChiselFunSpec with Utils { annos should contain(MarkAnnotation("~Top|Top/i:HasMems>mem".rt, "Mem")) annos should contain(MarkAnnotation("~Top|Top/i:HasMems>syncReadMem".rt, "SyncReadMem")) } + it("(3.p): should make connectable IOs on nested IsInstantiables that have IO Datas in them") { + val (chirrtl, _) = getFirrtlAndAnnos(new AddTwoNestedInstantiableData(4)) + exactly(3, chirrtl.serialize.split('\n')) should include("i1.in <= i0.out") + } + it( + "(3.q): should make connectable IOs on nested IsInstantiables's Data when the Instance and Definition do not have the same parent" + ) { + val (chirrtl, _) = getFirrtlAndAnnos(new AddTwoNestedInstantiableDataWrapper(4)) + exactly(3, chirrtl.serialize.split('\n')) should include("i1.in <= i0.out") + } } describe("4: toInstance") { it("4.0: should work on modules") { |