1 files changed, 26 insertions, 27 deletions

diff --git a/src/test/scala/chiselTests/When.scala b/src/test/scala/chiselTests/When.scala
index 3b5ec62e..032a8eac 100644
--- a/src/test/scala/chiselTests/When.scala
+++ b/src/test/scala/chiselTests/When.scala
@@ -14,11 +14,11 @@ class WhenTester() extends BasicTester {
   val out = Wire(UInt(3.W))
   when(cnt.value === 0.U) {
     out := 1.U
-  } .elsewhen (cnt.value === 1.U) {
+  }.elsewhen(cnt.value === 1.U) {
     out := 2.U
-  } .elsewhen (cnt.value === 2.U) {
+  }.elsewhen(cnt.value === 2.U) {
     out := 3.U
-  } .otherwise {
+  }.otherwise {
     out := 0.U
   }
 
@@ -36,11 +36,11 @@ class OverlappedWhenTester() extends BasicTester {
   val out = Wire(UInt(3.W))
   when(cnt.value <= 0.U) {
     out := 1.U
-  } .elsewhen (cnt.value <= 1.U) {
+  }.elsewhen(cnt.value <= 1.U) {
     out := 2.U
-  } .elsewhen (cnt.value <= 2.U) {
+  }.elsewhen(cnt.value <= 2.U) {
     out := 3.U
-  } .otherwise {
+  }.otherwise {
     out := 0.U
   }
 
@@ -58,13 +58,13 @@ class NoOtherwiseOverlappedWhenTester() extends BasicTester {
   val out = Wire(UInt(3.W))
   when(cnt.value <= 0.U) {
     out := 1.U
-  } .elsewhen (cnt.value <= 1.U) {
+  }.elsewhen(cnt.value <= 1.U) {
     out := 2.U
-  } .elsewhen (cnt.value <= 2.U) {
+  }.elsewhen(cnt.value <= 2.U) {
     out := 3.U
-  } .elsewhen (cnt.value <= 3.U) {
+  }.elsewhen(cnt.value <= 3.U) {
     out := 0.U
-  } .otherwise {
+  }.otherwise {
     out := DontCare
   }
 
@@ -77,15 +77,14 @@ class NoOtherwiseOverlappedWhenTester() extends BasicTester {
 
 class SubmoduleWhenTester extends BasicTester {
   val (cycle, done) = Counter(true.B, 3)
-  when (done) { stop() }
-  val children = Seq(Module(new PassthroughModule),
-                     Module(new PassthroughMultiIOModule),
-                     Module(new PassthroughRawModule))
+  when(done) { stop() }
+  val children =
+    Seq(Module(new PassthroughModule), Module(new PassthroughMultiIOModule), Module(new PassthroughRawModule))
   children.foreach { child =>
-    when (cycle === 1.U) {
+    when(cycle === 1.U) {
       child.io.in := "hdeadbeef".U
       assert(child.io.out === "hdeadbeef".U)
-    } .otherwise {
+    }.otherwise {
       child.io.in := "h0badcad0".U
       assert(child.io.out === "h0badcad0".U)
     }
@@ -97,17 +96,17 @@ class WhenCondTester extends BasicTester {
   val (cycle, done) = Counter(true.B, 1 << pred.size)
   // Cycle through every predicate
   pred := cycle.asBools
-  val Seq(a, b, c, d) = pred  // Just for nicer accessors
+  val Seq(a, b, c, d) = pred // Just for nicer accessors
   // When want the when predicates on connection to optimize away,
   //   it's not necessary but it makes the Verilog prettier
   val w1, w2, w3, w4, w5, w6, w7 = WireInit(Bool(), DontCare)
-  when (a) {
+  when(a) {
     w1 := when.cond
-    when (b) {
+    when(b) {
       w2 := when.cond
-    }.elsewhen (c) {
+    }.elsewhen(c) {
       w3 := when.cond
-    }.elsewhen (d) {
+    }.elsewhen(d) {
       w4 := when.cond
     }.otherwise {
       w5 := when.cond
@@ -125,18 +124,18 @@ class WhenCondTester extends BasicTester {
   assert(w6 === !a)
   assert(w7)
 
-  when (done) { stop() }
+  when(done) { stop() }
 }
 
 class WhenSpec extends ChiselFlatSpec with Utils {
   "When, elsewhen, and otherwise with orthogonal conditions" should "work" in {
-    assertTesterPasses{ new WhenTester }
+    assertTesterPasses { new WhenTester }
   }
   "When, elsewhen, and otherwise with overlapped conditions" should "work" in {
-    assertTesterPasses{ new OverlappedWhenTester }
+    assertTesterPasses { new OverlappedWhenTester }
   }
   "When and elsewhen without otherwise with overlapped conditions" should "work" in {
-    assertTesterPasses{ new NoOtherwiseOverlappedWhenTester }
+    assertTesterPasses { new NoOtherwiseOverlappedWhenTester }
   }
   "Conditional connections to submodule ports" should "be handled properly" in {
     assertTesterPasses(new SubmoduleWhenTester)
@@ -146,7 +145,7 @@ class WhenSpec extends ChiselFlatSpec with Utils {
   }
 
   "Returning in a when scope" should "give a reasonable error message" in {
-    val e = the [ChiselException] thrownBy extractCause[ChiselException] {
+    val e = the[ChiselException] thrownBy extractCause[ChiselException] {
       ChiselStage.elaborate(new Module {
         val io = IO(new Bundle {
           val foo = Input(UInt(8.W))
@@ -164,6 +163,6 @@ class WhenSpec extends ChiselFlatSpec with Utils {
         io.out := func()
       })
     }
-    e.getMessage should include ("Cannot exit from a when() block with a \"return\"")
+    e.getMessage should include("Cannot exit from a when() block with a \"return\"")
   }
 }