1 files changed, 6 insertions, 5 deletions
diff --git a/src/test/scala/chiselTests/SwitchSpec.scala b/src/test/scala/chiselTests/SwitchSpec.scala
index 2991a928..79849c76 100644
--- a/src/test/scala/chiselTests/SwitchSpec.scala
+++ b/src/test/scala/chiselTests/SwitchSpec.scala
@@ -3,12 +3,13 @@
 package chiselTests
 
 import chisel3._
+import chisel3.stage.ChiselStage
 import chisel3.util._
 
-class SwitchSpec extends ChiselFlatSpec {
+class SwitchSpec extends ChiselFlatSpec with Utils {
   "switch" should "require literal conditions" in {
-    a [java.lang.IllegalArgumentException] should be thrownBy {
-      elaborate(new Module {
+    a [java.lang.IllegalArgumentException] should be thrownBy extractCause[IllegalArgumentException] {
+      ChiselStage.elaborate(new Module {
         val io = IO(new Bundle {})
         val state = RegInit(0.U)
         val wire = WireDefault(0.U)
@@ -19,8 +20,8 @@ class SwitchSpec extends ChiselFlatSpec {
     }
   }
   it should "require mutually exclusive conditions" in {
-    a [java.lang.IllegalArgumentException] should be thrownBy {
-      elaborate(new Module {
+    a [java.lang.IllegalArgumentException] should be thrownBy extractCause[IllegalArgumentException] {
+      ChiselStage.elaborate(new Module {
         val io = IO(new Bundle {})
         val state = RegInit(0.U)
         switch (state) {