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-rw-r--r--src/test/scala/chiselTests/Stack.scala22
1 files changed, 11 insertions, 11 deletions
diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala
index a72af928..58a05937 100644
--- a/src/test/scala/chiselTests/Stack.scala
+++ b/src/test/scala/chiselTests/Stack.scala
@@ -12,23 +12,23 @@ class ChiselStack(val depth: Int) extends Module {
val push = Input(Bool())
val pop = Input(Bool())
val en = Input(Bool())
- val dataIn = Input(UInt.width(32))
- val dataOut = Output(UInt.width(32))
+ val dataIn = Input(UInt(32.W))
+ val dataOut = Output(UInt(32.W))
})
- val stack_mem = Mem(depth, UInt.width(32))
- val sp = Reg(init = UInt(0, width = log2Up(depth + 1)))
- val out = Reg(init = UInt(0, width = 32))
+ val stack_mem = Mem(depth, UInt(32.W))
+ val sp = Reg(init = 0.U(log2Up(depth+1).W))
+ val out = Reg(init = 0.U(32.W))
when (io.en) {
- when(io.push && (sp < UInt(depth))) {
+ when(io.push && (sp < depth.asUInt)) {
stack_mem(sp) := io.dataIn
- sp := sp +% UInt(1)
- } .elsewhen(io.pop && (sp > UInt(0))) {
- sp := sp -% UInt(1)
+ sp := sp +% 1.U
+ } .elsewhen(io.pop && (sp > 0.U)) {
+ sp := sp -% 1.U
}
- when (sp > UInt(0)) {
- out := stack_mem(sp -% UInt(1))
+ when (sp > 0.U) {
+ out := stack_mem(sp -% 1.U)
}
}
io.dataOut := out