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-rw-r--r--src/test/scala/chiselTests/Risc.scala16
1 files changed, 8 insertions, 8 deletions
diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala
index 3daa5bd2..670aa703 100644
--- a/src/test/scala/chiselTests/Risc.scala
+++ b/src/test/scala/chiselTests/Risc.scala
@@ -4,14 +4,14 @@ package chiselTests
import Chisel._
class Risc extends Module {
- val io = new Bundle {
- val isWr = Bool(INPUT)
- val wrAddr = UInt(INPUT, 8)
- val wrData = Bits(INPUT, 32)
- val boot = Bool(INPUT)
- val valid = Bool(OUTPUT)
- val out = Bits(OUTPUT, 32)
- }
+ val io = IO(new Bundle {
+ val isWr = Input(Bool())
+ val wrAddr = Input(UInt(8))
+ val wrData = Input(Bits(32))
+ val boot = Input(Bool())
+ val valid = Output(Bool())
+ val out = Output(Bits(32))
+ })
val memSize = 256
val file = Mem(memSize, Bits(width = 32))
val code = Mem(memSize, Bits(width = 32))