1 files changed, 11 insertions, 11 deletions
diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala
index 6d5a0a76..ae99df59 100644
--- a/src/test/scala/chiselTests/Risc.scala
+++ b/src/test/scala/chiselTests/Risc.scala
@@ -8,18 +8,18 @@ import chisel3.util._
 class Risc extends Module {
   val io = IO(new Bundle {
     val isWr   = Input(Bool())
-    val wrAddr = Input(UInt.width(8))
-    val wrData = Input(Bits.width(32))
+    val wrAddr = Input(UInt(8.W))
+    val wrData = Input(Bits(32.W))
     val boot   = Input(Bool())
     val valid  = Output(Bool())
-    val out    = Output(Bits.width(32))
+    val out    = Output(Bits(32.W))
   })
   val memSize = 256
-  val file = Mem(memSize, Bits.width(32))
-  val code = Mem(memSize, Bits.width(32))
-  val pc   = Reg(init=UInt(0, 8))
+  val file = Mem(memSize, Bits(32.W))
+  val code = Mem(memSize, Bits(32.W))
+  val pc   = Reg(init=0.U(8.W))
 
-  val add_op :: imm_op :: Nil = Enum(Bits.width(8), 2)
+  val add_op :: imm_op :: Nil = Enum(Bits(8.W), 2)
 
   val inst = code(pc)
   val op   = inst(31,24)
@@ -29,16 +29,16 @@ class Risc extends Module {
 
   val ra = Mux(rai === 0.asUInt(), 0.asUInt(), file(rai))
   val rb = Mux(rbi === 0.asUInt(), 0.asUInt(), file(rbi))
-  val rc = Wire(Bits.width(32))
+  val rc = Wire(Bits(32.W))
 
-  io.valid := Bool(false)
+  io.valid := false.B
   io.out   := 0.asUInt()
   rc       := 0.asUInt()
 
   when (io.isWr) {
     code(io.wrAddr) := io.wrData
   } .elsewhen (io.boot) {
-    pc := UInt(0)
+    pc := 0.U
   } .otherwise {
     switch(op) {
       is(add_op) { rc := ra +% rb }
@@ -46,7 +46,7 @@ class Risc extends Module {
     }
     io.out := rc
     when (rci === 255.asUInt()) {
-      io.valid := Bool(true)
+      io.valid := true.B
     } .otherwise {
       file(rci) := rc
     }