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Diffstat (limited to 'src/test/scala/chiselTests/ResetSpec.scala')
| -rw-r--r-- | src/test/scala/chiselTests/ResetSpec.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/test/scala/chiselTests/ResetSpec.scala b/src/test/scala/chiselTests/ResetSpec.scala index 9d67637d..84d3985b 100644 --- a/src/test/scala/chiselTests/ResetSpec.scala +++ b/src/test/scala/chiselTests/ResetSpec.scala @@ -73,14 +73,14 @@ class ResetSpec extends ChiselFlatSpec with Utils { behavior of "Users" they should "be able to force implicit reset to be synchronous" in { - val fir = (new ChiselStage).emitChirrtl(new MultiIOModule with RequireSyncReset { + val fir = ChiselStage.emitChirrtl(new MultiIOModule with RequireSyncReset { reset shouldBe a [Bool] }) fir should include ("input reset : UInt<1>") } they should "be able to force implicit reset to be asynchronous" in { - val fir = (new ChiselStage).emitChirrtl(new MultiIOModule with RequireAsyncReset { + val fir = ChiselStage.emitChirrtl(new MultiIOModule with RequireAsyncReset { reset shouldBe an [AsyncReset] }) fir should include ("input reset : AsyncReset") |