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Diffstat (limited to 'src/test/scala/chiselTests/Reg.scala')
| -rw-r--r-- | src/test/scala/chiselTests/Reg.scala | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala index c4df0742..576c7501 100644 --- a/src/test/scala/chiselTests/Reg.scala +++ b/src/test/scala/chiselTests/Reg.scala @@ -5,6 +5,7 @@ package chiselTests import chisel3._ import chisel3.util._ import chisel3.experimental.DataMirror +import chisel3.stage.ChiselStage import chisel3.testers.BasicTester class RegSpec extends ChiselFlatSpec { @@ -13,7 +14,7 @@ class RegSpec extends ChiselFlatSpec { val reg = Reg(UInt(2.W)) DataMirror.widthOf(reg) should be (2.W) } - elaborate{ new RegOutTypeWidthTester } + ChiselStage.elaborate{ new RegOutTypeWidthTester } } "RegNext" should "be of unknown width" in { @@ -25,7 +26,7 @@ class RegSpec extends ChiselFlatSpec { val reg3 = RegNext(2.U(3.W), 4.U(5.W)) DataMirror.widthOf(reg3).known should be (false) } - elaborate { new RegUnknownWidthTester } + ChiselStage.elaborate { new RegUnknownWidthTester } } "RegInit" should "have width only if specified in the literal" in { @@ -35,7 +36,7 @@ class RegSpec extends ChiselFlatSpec { val reg2 = RegInit(20.U(7.W)) DataMirror.widthOf(reg2) should be (7.W) } - elaborate{ new RegForcedWidthTester } + ChiselStage.elaborate{ new RegForcedWidthTester } } } |