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Diffstat (limited to 'src/test/scala/chiselTests/MultiClockSpec.scala')
| -rw-r--r-- | src/test/scala/chiselTests/MultiClockSpec.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/test/scala/chiselTests/MultiClockSpec.scala b/src/test/scala/chiselTests/MultiClockSpec.scala index 1a71570d..0b9497b8 100644 --- a/src/test/scala/chiselTests/MultiClockSpec.scala +++ b/src/test/scala/chiselTests/MultiClockSpec.scala @@ -4,7 +4,7 @@ package chiselTests import chisel3._ import chisel3.util.Counter -import chisel3.testers.BasicTester +import chisel3.testers.{BasicTester, TesterDriver} import chisel3.stage.ChiselStage /** Multi-clock test of a Reg using a different clock via withClock */ @@ -120,7 +120,7 @@ class MultiClockSpec extends ChiselFlatSpec { } it should "scope ports of memories" in { - assertTesterPasses(new MultiClockMemTest) + assertTesterPasses(new MultiClockMemTest, annotations = TesterDriver.verilatorOnly) } it should "return like a normal Scala block" in { |