1 files changed, 18 insertions, 18 deletions

diff --git a/src/test/scala/chiselTests/MultiClockSpec.scala b/src/test/scala/chiselTests/MultiClockSpec.scala
index 3b52e5b9..2553f3b3 100644
--- a/src/test/scala/chiselTests/MultiClockSpec.scala
+++ b/src/test/scala/chiselTests/MultiClockSpec.scala
@@ -18,11 +18,11 @@ class ClockDividerTest extends BasicTester {
   val reg2 = withClock(clock2) { RegInit(0.U(8.W)) }
   reg2 := reg2 + 1.U
 
-  when (reg1 < 10.U) {
+  when(reg1 < 10.U) {
     assert(reg2 === reg1 / 2.U) // 1:2 clock relationship
   }
 
-  when (reg1 === 10.U) {
+  when(reg1 === 10.U) {
     stop()
   }
 }
@@ -45,7 +45,7 @@ class MultiClockSubModuleTest extends BasicTester {
 
   val inst = withClockAndReset(otherClock, otherReset) { Module(new SubModule) }
 
-  when (done) {
+  when(done) {
     // The counter in inst should come out of reset later and increment at half speed
     assert(inst.io.out === 3.U)
     stop()
@@ -59,14 +59,14 @@ class WithResetTest extends BasicTester {
   reg := reg + 1.U
 
   val (cycle, done) = Counter(true.B, 10)
-  when (cycle < 7.U) {
+  when(cycle < 7.U) {
     assert(reg === cycle)
-  } .elsewhen (cycle === 7.U) {
+  }.elsewhen(cycle === 7.U) {
     reset2 := true.B
-  } .elsewhen (cycle === 8.U) {
+  }.elsewhen(cycle === 8.U) {
     assert(reg === 0.U)
   }
-  when (done) { stop() }
+  when(done) { stop() }
 }
 
 /** Test Mem ports with different clocks */
@@ -82,7 +82,7 @@ class MultiClockMemTest extends BasicTester {
   // Write port 1 walks through writing 123
   val waddr = RegInit(0.U(3.W))
   waddr := waddr + 1.U
-  when (cycle < 8.U) {
+  when(cycle < 8.U) {
     mem(waddr) := 123.U
   }
 
@@ -90,27 +90,27 @@ class MultiClockMemTest extends BasicTester {
   val rdata = mem(raddr)
 
   // Check each write from write port 1
-  when (cycle > 0.U && cycle < 9.U) {
+  when(cycle > 0.U && cycle < 9.U) {
     assert(rdata === 123.U)
   }
 
   // Write port 2 walks through writing 456 on 2nd time through
   withClock(clock2) {
-    when (cycle >= 8.U && cycle < 16.U) {
+    when(cycle >= 8.U && cycle < 16.U) {
       mem(waddr) := 456.U // write 456 to different address
     }
   }
 
   // Check that every even address gets 456
-  when (cycle > 8.U && cycle < 17.U) {
-    when (raddr % 2.U === 0.U) {
+  when(cycle > 8.U && cycle < 17.U) {
+    when(raddr % 2.U === 0.U) {
       assert(rdata === 456.U)
-    } .otherwise {
+    }.otherwise {
       assert(rdata === 123.U)
     }
   }
 
-  when (done) { stop() }
+  when(done) { stop() }
 }
 
 class MultiClockSpec extends ChiselFlatSpec {
@@ -151,7 +151,7 @@ class MultiClockSpec extends ChiselFlatSpec {
       // The reg is always in reset so will never decrement
       chisel3.assert(reg === 6.U)
       val (_, done) = Counter(true.B, 4)
-      when (done) { stop() }
+      when(done) { stop() }
     })
   }
 
@@ -168,7 +168,7 @@ class MultiClockSpec extends ChiselFlatSpec {
         chisel3.assert(0.U === 1.U)
       }
       val (_, done) = Counter(true.B, 2)
-      when (done) { stop() }
+      when(done) { stop() }
     })
     // Check that reset will block
     assertTesterPasses(new BasicTester {
@@ -176,7 +176,7 @@ class MultiClockSpec extends ChiselFlatSpec {
         chisel3.assert(0.U === 1.U)
       }
       val (_, done) = Counter(true.B, 2)
-      when (done) { stop() }
+      when(done) { stop() }
     })
     // Check that no rising edge will block
     assertTesterPasses(new BasicTester {
@@ -184,7 +184,7 @@ class MultiClockSpec extends ChiselFlatSpec {
         chisel3.assert(0.U === 1.U)
       }
       val (_, done) = Counter(true.B, 2)
-      when (done) { stop() }
+      when(done) { stop() }
     })
   }
 }