diff options
Diffstat (limited to 'src/test/scala/chiselTests/LiteralToTargetSpec.scala')
| -rw-r--r-- | src/test/scala/chiselTests/LiteralToTargetSpec.scala | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/test/scala/chiselTests/LiteralToTargetSpec.scala b/src/test/scala/chiselTests/LiteralToTargetSpec.scala index 3c404f2d..b1caecfa 100644 --- a/src/test/scala/chiselTests/LiteralToTargetSpec.scala +++ b/src/test/scala/chiselTests/LiteralToTargetSpec.scala @@ -9,12 +9,11 @@ import org.scalatest._ import org.scalatest.freespec.AnyFreeSpec import org.scalatest.matchers.should.Matchers - class LiteralToTargetSpec extends AnyFreeSpec with Matchers { "Literal Data should fail to be converted to ReferenceTarget" in { - the [chisel3.internal.ChiselException] thrownBy { + (the[chisel3.internal.ChiselException] thrownBy { class Bar extends RawModule { val a = 1.U @@ -26,6 +25,6 @@ class LiteralToTargetSpec extends AnyFreeSpec with Matchers { } ChiselStage.elaborate(new Foo) - } should have message "Illegal component name: UInt<1>(\"h01\") (note: literals are illegal)" + } should have).message("Illegal component name: UInt<1>(\"h01\") (note: literals are illegal)") } } |
