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Diffstat (limited to 'src/test/scala/chiselTests/IntervalSpec.scala')
| -rw-r--r-- | src/test/scala/chiselTests/IntervalSpec.scala | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/test/scala/chiselTests/IntervalSpec.scala b/src/test/scala/chiselTests/IntervalSpec.scala index 1f813442..0babed41 100644 --- a/src/test/scala/chiselTests/IntervalSpec.scala +++ b/src/test/scala/chiselTests/IntervalSpec.scala @@ -19,7 +19,6 @@ import firrtl.{FIRRTLException, HighFirrtlCompiler, LowFirrtlCompiler, MiddleFir import org.scalatest.freespec.AnyFreeSpec import org.scalatest.matchers.should.Matchers -//scalastyle:off magic.number //noinspection TypeAnnotation object IntervalTestHelper { @@ -30,7 +29,6 @@ object IntervalTestHelper { * @param gen the generator for the module * @return the Verilog code as a string. */ - //scalastyle:off cyclomatic.complexity def makeFirrtl[T <: RawModule](compilerName: String)(gen: () => T): String = { (new ChiselStage) .execute(Array("--compiler", compilerName, |