1 files changed, 77 insertions, 45 deletions
diff --git a/src/test/scala/chiselTests/ConnectSpec.scala b/src/test/scala/chiselTests/ConnectSpec.scala
index f9ef5946..3a2b6d93 100644
--- a/src/test/scala/chiselTests/ConnectSpec.scala
+++ b/src/test/scala/chiselTests/ConnectSpec.scala
@@ -10,7 +10,7 @@ import chisel3.stage.ChiselStage
 import chisel3.testers.BasicTester
 
 abstract class CrossCheck extends Bundle {
-  val in: Data
+  val in:  Data
   val out: Data
 }
 
@@ -41,92 +41,120 @@ class CrossConnectTester(inType: Data, outType: Data) extends BasicTester {
 
 class ConnectSpec extends ChiselPropSpec with Utils {
   property("SInt := SInt should succeed") {
-    assertTesterPasses{ new CrossConnectTester(SInt(16.W), SInt(16.W)) }
+    assertTesterPasses { new CrossConnectTester(SInt(16.W), SInt(16.W)) }
   }
   property("SInt := UInt should fail") {
-    intercept[ChiselException]{
+    intercept[ChiselException] {
       extractCause[ChiselException] {
-        ChiselStage.elaborate { new CrossConnectTester(UInt(16.W), SInt(16.W)) } } }
+        ChiselStage.elaborate { new CrossConnectTester(UInt(16.W), SInt(16.W)) }
+      }
+    }
   }
   property("SInt := FixedPoint should fail") {
-    intercept[ChiselException]{
+    intercept[ChiselException] {
       extractCause[ChiselException] {
-        ChiselStage.elaborate { new CrossConnectTester(FixedPoint(16.W, 8.BP), UInt(16.W)) } } }
+        ChiselStage.elaborate { new CrossConnectTester(FixedPoint(16.W, 8.BP), UInt(16.W)) }
+      }
+    }
   }
   property("UInt := UInt should succeed") {
-    assertTesterPasses{ new CrossConnectTester(UInt(16.W), UInt(16.W)) }
+    assertTesterPasses { new CrossConnectTester(UInt(16.W), UInt(16.W)) }
   }
   property("UInt := SInt should fail") {
-    intercept[ChiselException]{
+    intercept[ChiselException] {
       extractCause[ChiselException] {
-        ChiselStage.elaborate { new CrossConnectTester(SInt(16.W), UInt(16.W)) } } }
+        ChiselStage.elaborate { new CrossConnectTester(SInt(16.W), UInt(16.W)) }
+      }
+    }
   }
   property("UInt := FixedPoint should fail") {
-    intercept[ChiselException]{
+    intercept[ChiselException] {
       extractCause[ChiselException] {
-        ChiselStage.elaborate { new CrossConnectTester(FixedPoint(16.W, 8.BP), UInt(16.W)) } } }
+        ChiselStage.elaborate { new CrossConnectTester(FixedPoint(16.W, 8.BP), UInt(16.W)) }
+      }
+    }
   }
 
   property("Clock := Clock should succeed") {
-    assertTesterPasses{ new CrossConnectTester(Clock(), Clock()) }
+    assertTesterPasses { new CrossConnectTester(Clock(), Clock()) }
   }
   property("Clock := UInt should fail") {
-    intercept[ChiselException]{
+    intercept[ChiselException] {
       extractCause[ChiselException] {
-        ChiselStage.elaborate { new CrossConnectTester(Clock(), UInt(16.W)) } } }
+        ChiselStage.elaborate { new CrossConnectTester(Clock(), UInt(16.W)) }
+      }
+    }
   }
 
   property("FixedPoint := FixedPoint should succeed") {
-    assertTesterPasses{ new CrossConnectTester(FixedPoint(16.W, 8.BP), FixedPoint(16.W, 8.BP)) }
+    assertTesterPasses { new CrossConnectTester(FixedPoint(16.W, 8.BP), FixedPoint(16.W, 8.BP)) }
   }
   property("FixedPoint := SInt should fail") {
-    intercept[ChiselException]{
+    intercept[ChiselException] {
       extractCause[ChiselException] {
-        ChiselStage.elaborate { new CrossConnectTester(SInt(16.W), FixedPoint(16.W, 8.BP)) } } }
+        ChiselStage.elaborate { new CrossConnectTester(SInt(16.W), FixedPoint(16.W, 8.BP)) }
+      }
+    }
   }
   property("FixedPoint := UInt should fail") {
-    intercept[ChiselException]{
+    intercept[ChiselException] {
       extractCause[ChiselException] {
-        ChiselStage.elaborate { new CrossConnectTester(UInt(16.W), FixedPoint(16.W, 8.BP)) } } }
+        ChiselStage.elaborate { new CrossConnectTester(UInt(16.W), FixedPoint(16.W, 8.BP)) }
+      }
+    }
   }
 
   property("Analog := Analog should fail") {
-    intercept[ChiselException]{
+    intercept[ChiselException] {
       extractCause[ChiselException] {
-        ChiselStage.elaborate { new CrossConnectTester(Analog(16.W), Analog(16.W)) } } }
+        ChiselStage.elaborate { new CrossConnectTester(Analog(16.W), Analog(16.W)) }
+      }
+    }
   }
   property("Analog := FixedPoint should fail") {
-    intercept[ChiselException]{
+    intercept[ChiselException] {
       extractCause[ChiselException] {
-        ChiselStage.elaborate { new CrossConnectTester(Analog(16.W), FixedPoint(16.W, 8.BP)) } } }
+        ChiselStage.elaborate { new CrossConnectTester(Analog(16.W), FixedPoint(16.W, 8.BP)) }
+      }
+    }
   }
   property("FixedPoint := Analog should fail") {
-    intercept[ChiselException]{
+    intercept[ChiselException] {
       extractCause[ChiselException] {
-        ChiselStage.elaborate { new CrossConnectTester(FixedPoint(16.W, 8.BP), Analog(16.W)) } } }
+        ChiselStage.elaborate { new CrossConnectTester(FixedPoint(16.W, 8.BP), Analog(16.W)) }
+      }
+    }
   }
   property("Analog := UInt should fail") {
-    intercept[ChiselException]{
+    intercept[ChiselException] {
       extractCause[ChiselException] {
-        ChiselStage.elaborate { new CrossConnectTester(Analog(16.W), UInt(16.W)) } } }
+        ChiselStage.elaborate { new CrossConnectTester(Analog(16.W), UInt(16.W)) }
+      }
+    }
   }
   property("Analog := SInt should fail") {
-    intercept[ChiselException]{
+    intercept[ChiselException] {
       extractCause[ChiselException] {
-        ChiselStage.elaborate { new CrossConnectTester(Analog(16.W), SInt(16.W)) } } }
+        ChiselStage.elaborate { new CrossConnectTester(Analog(16.W), SInt(16.W)) }
+      }
+    }
   }
   property("UInt := Analog should fail") {
-    intercept[ChiselException]{
+    intercept[ChiselException] {
       extractCause[ChiselException] {
-        ChiselStage.elaborate { new CrossConnectTester(UInt(16.W), Analog(16.W)) } } }
+        ChiselStage.elaborate { new CrossConnectTester(UInt(16.W), Analog(16.W)) }
+      }
+    }
   }
   property("SInt := Analog should fail") {
-    intercept[ChiselException]{
+    intercept[ChiselException] {
       extractCause[ChiselException] {
-        ChiselStage.elaborate { new CrossConnectTester(SInt(16.W), Analog(16.W)) } } }
+        ChiselStage.elaborate { new CrossConnectTester(SInt(16.W), Analog(16.W)) }
+      }
+    }
   }
   property("Pipe internal connections should succeed") {
-    ChiselStage.elaborate( new PipeInternalWires)
+    ChiselStage.elaborate(new PipeInternalWires)
   }
 
   property("Connect error messages should have meaningful information") {
@@ -139,9 +167,9 @@ class ConnectSpec extends ChiselPropSpec with Utils {
       inner.myReg := false.B // ERROR
     }
 
-    val assignError = the [ChiselException] thrownBy {ChiselStage.elaborate { new OuterAssignExample}}
+    val assignError = the[ChiselException] thrownBy { ChiselStage.elaborate { new OuterAssignExample } }
     val expectedAssignError = """.*@: myReg in InnerExample cannot be written from module OuterAssignExample."""
-    assignError.getMessage should fullyMatch regex expectedAssignError
+    (assignError.getMessage should fullyMatch).regex(expectedAssignError)
 
     class OuterReadExample extends Module {
       val myReg = RegInit(0.U(8.W))
@@ -149,16 +177,20 @@ class ConnectSpec extends ChiselPropSpec with Utils {
       myReg := inner.myReg // ERROR
     }
 
-    val readError = the [ChiselException] thrownBy {ChiselStage.elaborate { new OuterReadExample }}
+    val readError = the[ChiselException] thrownBy { ChiselStage.elaborate { new OuterReadExample } }
     val expectedReadError = """.*@: myReg in InnerExample cannot be read from module OuterReadExample."""
-    readError.getMessage should fullyMatch regex expectedReadError
-
-    val typeMismatchError = the [ChiselException] thrownBy {ChiselStage.elaborate { new RawModule {
-      val myUInt = Wire(UInt(4.W))
-      val mySInt = Wire(SInt(4.W))
-      myUInt := mySInt
-    }}}
+    (readError.getMessage should fullyMatch).regex(expectedReadError)
+
+    val typeMismatchError = the[ChiselException] thrownBy {
+      ChiselStage.elaborate {
+        new RawModule {
+          val myUInt = Wire(UInt(4.W))
+          val mySInt = Wire(SInt(4.W))
+          myUInt := mySInt
+        }
+      }
+    }
     val expectedTypeMismatchError = """.*@: Sink \(UInt<4>\) and Source \(SInt<4>\) have different types."""
-    typeMismatchError.getMessage should fullyMatch regex expectedTypeMismatchError
+    (typeMismatchError.getMessage should fullyMatch).regex(expectedTypeMismatchError)
   }
 }