1 files changed, 17 insertions, 16 deletions
diff --git a/src/test/scala/chiselTests/CompileOptionsTest.scala b/src/test/scala/chiselTests/CompileOptionsTest.scala
index 10be4ffb..1bd0327a 100644
--- a/src/test/scala/chiselTests/CompileOptionsTest.scala
+++ b/src/test/scala/chiselTests/CompileOptionsTest.scala
@@ -4,8 +4,9 @@ package chiselTests
 
 import chisel3._
 import chisel3.CompileOptions._
+import chisel3.stage.ChiselStage
 
-class CompileOptionsSpec extends ChiselFlatSpec {
+class CompileOptionsSpec extends ChiselFlatSpec with Utils {
 
   abstract class StrictModule extends Module()(chisel3.ExplicitCompileOptions.Strict)
   abstract class NotStrictModule extends Module()(chisel3.ExplicitCompileOptions.NotStrict)
@@ -22,7 +23,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 
   // scalastyle:off line.size.limit
   "A Module with missing bundle fields when compiled with implicit Strict.CompileOption " should "throw an exception" in {
-    a [ChiselException] should be thrownBy {
+    a [ChiselException] should be thrownBy extractCause[ChiselException] {
       import chisel3.ExplicitCompileOptions.Strict
 
       class ConnectFieldMismatchModule extends Module {
@@ -32,7 +33,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
         })
         io.out := io.in
       }
-      elaborate { new ConnectFieldMismatchModule() }
+      ChiselStage.elaborate { new ConnectFieldMismatchModule() }
     }
   }
 
@@ -46,11 +47,11 @@ class CompileOptionsSpec extends ChiselFlatSpec {
       })
       io.out := io.in
     }
-    elaborate { new ConnectFieldMismatchModule() }
+    ChiselStage.elaborate { new ConnectFieldMismatchModule() }
   }
 
   "A Module in which a Reg is created with a bound type when compiled with implicit Strict.CompileOption " should "throw an exception" in {
-    a [BindingException] should be thrownBy {
+    a [BindingException] should be thrownBy extractCause[BindingException] {
       import chisel3.ExplicitCompileOptions.Strict
 
       class CreateRegFromBoundTypeModule extends Module {
@@ -60,7 +61,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
         })
         val badReg = Reg(7.U(4.W))
       }
-      elaborate { new CreateRegFromBoundTypeModule() }
+      ChiselStage.elaborate { new CreateRegFromBoundTypeModule() }
     }
   }
 
@@ -74,7 +75,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
       })
       val badReg = Reg(7.U(4.W))
     }
-    elaborate { new CreateRegFromBoundTypeModule() }
+    ChiselStage.elaborate { new CreateRegFromBoundTypeModule() }
   }
 
   "A Module with wrapped IO when compiled with implicit Strict.CompileOption " should "not throw an exception" in {
@@ -87,11 +88,11 @@ class CompileOptionsSpec extends ChiselFlatSpec {
       })
       io.out := io.in(1)
     }
-    elaborate { new RequireIOWrapModule() }
+    ChiselStage.elaborate { new RequireIOWrapModule() }
   }
 
   "A Module with unwrapped IO when compiled with implicit Strict.CompileOption " should "throw an exception" in {
-    a [BindingException] should be thrownBy {
+    a [BindingException] should be thrownBy extractCause[BindingException] {
       import chisel3.ExplicitCompileOptions.Strict
 
       class RequireIOWrapModule extends Module {
@@ -101,14 +102,14 @@ class CompileOptionsSpec extends ChiselFlatSpec {
         }
         io.out := io.in(1)
       }
-      elaborate {
+      ChiselStage.elaborate {
         new RequireIOWrapModule()
       }
     }
   }
 
   "A Module connecting output as source to input as sink when compiled with implicit Strict.CompileOption " should "throw an exception" in {
-    a [ChiselException] should be thrownBy {
+    a [ChiselException] should be thrownBy extractCause[ChiselException] {
       import chisel3.ExplicitCompileOptions.Strict
 
       class SimpleModule extends Module {
@@ -121,7 +122,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
         val child = Module(new SimpleModule)
         io.in := child.io.out
       }
-      elaborate { new SwappedConnectionModule() }
+      ChiselStage.elaborate { new SwappedConnectionModule() }
     }
   }
 
@@ -138,11 +139,11 @@ class CompileOptionsSpec extends ChiselFlatSpec {
       val child = Module(new SimpleModule)
       io.in := child.io.out
     }
-    elaborate { new SwappedConnectionModule() }
+    ChiselStage.elaborate { new SwappedConnectionModule() }
   }
 
   "A Module with directionless connections when compiled with implicit Strict.CompileOption " should "throw an exception" in {
-    a [ChiselException] should be thrownBy {
+    a [ChiselException] should be thrownBy extractCause[ChiselException] {
       // Verify we can suppress the inclusion of default compileOptions
       import Chisel.{defaultCompileOptions => _}
       import chisel3.ExplicitCompileOptions.Strict
@@ -161,7 +162,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
         val child = Module(new SimpleModule)
         b := child.noDir
       }
-      elaborate { new DirectionLessConnectionModule() }
+      ChiselStage.elaborate { new DirectionLessConnectionModule() }
     }
   }
 
@@ -182,7 +183,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
       val child = Module(new SimpleModule)
       b := child.noDir
     }
-    elaborate { new DirectionLessConnectionModule() }
+    ChiselStage.elaborate { new DirectionLessConnectionModule() }
   }
   // scalastyle:on line.size.limit
 }