1 files changed, 21 insertions, 2 deletions
diff --git a/src/test/scala/chiselTests/CompatibilitySpec.scala b/src/test/scala/chiselTests/CompatibilitySpec.scala
index d134c380..41cfbec4 100644
--- a/src/test/scala/chiselTests/CompatibilitySpec.scala
+++ b/src/test/scala/chiselTests/CompatibilitySpec.scala
@@ -238,10 +238,10 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
 
   "A Module without val io" should "throw an exception" in {
     class ModuleWithoutValIO extends Module {
-      val foo = new Bundle {
+      val foo = IO(new Bundle {
         val in = UInt(width = 32).asInput
         val out = Bool().asOutput
-      }
+      })
       foo.out := foo.in(1)
     }
     val e = intercept[Exception](
@@ -595,4 +595,23 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
     verilog should include("output [7:0] io_bar")
   }
 
+  it should "properly handle hardware construction before val io is initialized" in {
+    class MyModule extends Module {
+      val foo = Wire(init = UInt(8))
+      val io = new Bundle {
+        val in = UInt(INPUT, width = 8)
+        val en = Bool(INPUT)
+        val out = UInt(OUTPUT, width = 8)
+      }
+      io.out := foo
+      when(io.en) {
+        io.out := io.in
+      }
+    }
+    // Just check that this doesn't crash during elaboration. For more info see:
+    // https://github.com/chipsalliance/chisel3/issues/1802
+    //
+    ChiselStage.elaborate(new MyModule)
+  }
+
 }