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Diffstat (limited to 'src/test/scala/chiselTests/Clock.scala')
| -rw-r--r-- | src/test/scala/chiselTests/Clock.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/Clock.scala b/src/test/scala/chiselTests/Clock.scala index 4b10d3b4..b6c9adc1 100644 --- a/src/test/scala/chiselTests/Clock.scala +++ b/src/test/scala/chiselTests/Clock.scala @@ -31,7 +31,7 @@ class ClockSpec extends ChiselPropSpec { } property("Should be able to use withClock in a module with no reset") { - val circuit = (new ChiselStage).emitChirrtl(new WithClockAndNoReset) + val circuit = ChiselStage.emitChirrtl(new WithClockAndNoReset) circuit.contains("reg a : UInt<1>, clock2") should be (true) } } |