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-rw-r--r--src/test/scala/chiselTests/BetterNamingTests.scala5
1 files changed, 2 insertions, 3 deletions
diff --git a/src/test/scala/chiselTests/BetterNamingTests.scala b/src/test/scala/chiselTests/BetterNamingTests.scala
index dd17a015..9c309091 100644
--- a/src/test/scala/chiselTests/BetterNamingTests.scala
+++ b/src/test/scala/chiselTests/BetterNamingTests.scala
@@ -90,9 +90,8 @@ class BetterNamingTests extends ChiselFlatSpec {
}
WireDefault(3.U)
}
- val stage = new ChiselStage
- val withLits = stage.emitChirrtl(new MyModule(true))
- val noLits = stage.emitChirrtl(new MyModule(false))
+ val withLits = ChiselStage.emitChirrtl(new MyModule(true))
+ val noLits = ChiselStage.emitChirrtl(new MyModule(false))
withLits should equal (noLits)
}
}