1 files changed, 23 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/AnalogSpec.scala b/src/test/scala/chiselTests/AnalogSpec.scala
index b262074c..c78c8c0e 100644
--- a/src/test/scala/chiselTests/AnalogSpec.scala
+++ b/src/test/scala/chiselTests/AnalogSpec.scala
@@ -169,6 +169,29 @@ class AnalogSpec extends ChiselFlatSpec {
         wires(0) <> wires(2)
       })
     }
+    a [ChiselException] should be thrownBy {
+      elaborate(new Module {
+        val io = IO(new Bundle {})
+        val wires = List.fill(2)(Wire(Analog(32.W)))
+        wires(0) <> DontCare
+        wires(0) <> wires(1)
+      })
+    }
+  }
+
+  it should "allow DontCare connection" in {
+    elaborate(new Module {
+      val io = IO(new Bundle {
+        val a = Analog(1.W)
+      })
+      io.a := DontCare
+    })
+    elaborate(new Module {
+      val io = IO(new Bundle {
+        val a = Analog(1.W)
+      })
+      io.a <> DontCare
+    })
   }
 
   it should "work with 3 blackboxes attached" in {