2 files changed, 3 insertions, 6 deletions
diff --git a/src/main/scala/Chisel/Aggregate.scala b/src/main/scala/Chisel/Aggregate.scala
index 3df48052..6bf656a9 100644
--- a/src/main/scala/Chisel/Aggregate.scala
+++ b/src/main/scala/Chisel/Aggregate.scala
@@ -46,8 +46,7 @@ object Vec {
 
     require(!elts.isEmpty)
     val width = elts.map(_.width).reduce(_ max _)
-    val vec = new Vec(elts.head.cloneTypeWidth(width), elts.length)
-    pushCommand(DefWire(vec))
+    val vec = Wire(new Vec(elts.head.cloneTypeWidth(width), elts.length))
     for ((v, e) <- vec zip elts)
       v := e
     vec
diff --git a/src/main/scala/Chisel/Data.scala b/src/main/scala/Chisel/Data.scala
index fa6e5729..ac3bd9ab 100644
--- a/src/main/scala/Chisel/Data.scala
+++ b/src/main/scala/Chisel/Data.scala
@@ -123,11 +123,9 @@ object Wire {
   private def makeWire[T <: Data](t: T, init: T): T = {
     val x = Reg.makeType(t, null.asInstanceOf[T], init)
     pushCommand(DefWire(x))
-    if (init != null) {
+    pushCommand(DefInvalid(x.ref))
+    if (init != null)
       x := init
-    } else {
-      pushCommand(DefInvalid(x.ref))
-    }
     x
   }
 }