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Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/Chisel/Core.scala | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/main/scala/Chisel/Core.scala b/src/main/scala/Chisel/Core.scala index 4b8d2ca3..1ab84681 100644 --- a/src/main/scala/Chisel/Core.scala +++ b/src/main/scala/Chisel/Core.scala @@ -639,7 +639,11 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg: def asUInt(): UInt final def toSInt(): SInt = asSInt final def toUInt(): UInt = asUInt - def toBool(): Bool = this(0) + + def toBool(): Bool = width match { + case KnownWidth(1) => this(0) + case _ => throwException(s"can't covert UInt<$width> to Bool") + } override def toBits = asUInt override def fromBits(n: Bits): this.type = { |