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-rw-r--r--src/main/scala/chisel3/compatibility.scala88
-rw-r--r--src/main/scala/chisel3/package.scala79
-rw-r--r--src/main/scala/chisel3/testers/BasicTester.scala2
-rw-r--r--src/main/scala/chisel3/util/Arbiter.scala10
-rw-r--r--src/main/scala/chisel3/util/BitPat.scala4
-rw-r--r--src/main/scala/chisel3/util/Bitwise.scala2
-rw-r--r--src/main/scala/chisel3/util/CircuitMath.scala2
-rw-r--r--src/main/scala/chisel3/util/Decoupled.scala117
-rw-r--r--src/main/scala/chisel3/util/Reg.scala3
-rw-r--r--src/main/scala/chisel3/util/Valid.scala30
10 files changed, 221 insertions, 116 deletions
diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index 56c92d24..5624b79c 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -5,11 +5,14 @@
package object Chisel {
type Direction = chisel3.core.Direction
- val INPUT = chisel3.core.INPUT
- val OUTPUT = chisel3.core.OUTPUT
- val NO_DIR = chisel3.core.NO_DIR
+ val INPUT = chisel3.core.Direction.Input
+ val OUTPUT = chisel3.core.Direction.Output
+ val NODIR = chisel3.core.Direction.Unspecified
+ object Flipped {
+ def apply[T<:Data](target: T): T = chisel3.core.Flipped[T](target)
+ }
+ type ChiselException = chisel3.internal.ChiselException
- type Flipped = chisel3.core.Flipped
type Data = chisel3.core.Data
val Wire = chisel3.core.Wire
val Clock = chisel3.core.Clock
@@ -54,6 +57,46 @@ package object Chisel {
val when = chisel3.core.when
type WhenContext = chisel3.core.WhenContext
+ import chisel3.internal.firrtl.Width
+ /**
+ * These implicit classes allow one to convert scala.Int|scala.BigInt to
+ * Chisel.UInt|Chisel.SInt by calling .asUInt|.asSInt on them, respectively.
+ * The versions .asUInt(width)|.asSInt(width) are also available to explicitly
+ * mark a width for the new literal.
+ *
+ * Also provides .asBool to scala.Boolean and .asUInt to String
+ *
+ * Note that, for stylistic reasons, one should avoid extracting immediately
+ * after this call using apply, ie. 0.asUInt(1)(0) due to potential for
+ * confusion (the 1 is a bit length and the 0 is a bit extraction position).
+ * Prefer storing the result and then extracting from it.
+ */
+ implicit class fromIntToLiteral(val x: Int) extends AnyVal {
+ def U: UInt = UInt(BigInt(x), Width())
+ def S: SInt = SInt(BigInt(x), Width())
+
+ def asUInt() = UInt(x, Width())
+ def asSInt() = SInt(x, Width())
+ def asUInt(width: Int) = UInt(x, width)
+ def asSInt(width: Int) = SInt(x, width)
+ }
+
+ implicit class fromBigIntToLiteral(val x: BigInt) extends AnyVal {
+ def U: UInt = UInt(x, Width())
+ def S: SInt = SInt(x, Width())
+
+ def asUInt() = UInt(x, Width())
+ def asSInt() = SInt(x, Width())
+ def asUInt(width: Int) = UInt(x, width)
+ def asSInt(width: Int) = SInt(x, width)
+ }
+ implicit class fromStringToLiteral(val x: String) extends AnyVal {
+ def U: UInt = UInt(x)
+ }
+ implicit class fromBooleanToLiteral(val x: Boolean) extends AnyVal {
+ def B: Bool = Bool(x)
+ }
+
type BackendCompilationUtilities = chisel3.BackendCompilationUtilities
val Driver = chisel3.Driver
@@ -102,10 +145,27 @@ package object Chisel {
val Counter = chisel3.util.Counter
type DecoupledIO[+T <: Data] = chisel3.util.DecoupledIO[T]
- val Decoupled = chisel3.util.Decoupled
- type EnqIO[T <: Data] = chisel3.util.EnqIO[T]
- type DeqIO[T <: Data] = chisel3.util.DeqIO[T]
- type DecoupledIOC[+T <: Data] = chisel3.util.DecoupledIOC[T]
+ val DecoupledIO = chisel3.util.DecoupledIO
+ val Decoupled = chisel3.util.DecoupledIO
+ class EnqIO[+T <: Data](gen: T) extends DecoupledIO(gen) {
+ def init(): Unit = {
+ this.noenq()
+ }
+ override def cloneType: this.type = EnqIO(gen).asInstanceOf[this.type]
+ }
+ class DeqIO[+T <: Data](gen: T) extends DecoupledIO(gen) {
+ chisel3.core.Binding.bind(this, chisel3.core.FlippedBinder, "Error: Cannot flip ")
+ def init(): Unit = {
+ this.nodeq()
+ }
+ override def cloneType: this.type = DeqIO(gen).asInstanceOf[this.type]
+ }
+ object EnqIO {
+ def apply[T<:Data](gen: T): DecoupledIO[T] = DecoupledIO(gen)
+ }
+ object DeqIO {
+ def apply[T<:Data](gen: T): DecoupledIO[T] = Flipped(DecoupledIO(gen))
+ }
type QueueIO[T <: Data] = chisel3.util.QueueIO[T]
type Queue[T <: Data] = chisel3.util.Queue[T]
val Queue = chisel3.util.Queue
@@ -132,19 +192,9 @@ package object Chisel {
val RegEnable = chisel3.util.RegEnable
val ShiftRegister = chisel3.util.ShiftRegister
- type ValidIO[+T <: Data] = chisel3.util.ValidIO[T]
+ type ValidIO[+T <: Data] = chisel3.util.Valid[T]
val Valid = chisel3.util.Valid
val Pipe = chisel3.util.Pipe
type Pipe[T <: Data] = chisel3.util.Pipe[T]
-
- import chisel3.internal.firrtl.Width
- implicit def fromBigIntToLiteral(x: BigInt): chisel3.fromBigIntToLiteral =
- new chisel3.fromBigIntToLiteral(x)
- implicit def fromIntToLiteral(x: Int): chisel3.fromIntToLiteral=
- new chisel3.fromIntToLiteral(x)
- implicit def fromStringToLiteral(x: String): chisel3.fromStringToLiteral=
- new chisel3.fromStringToLiteral(x)
- implicit def fromBooleanToLiteral(x: Boolean): chisel3.fromBooleanToLiteral=
- new chisel3.fromBooleanToLiteral(x)
}
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 0b548683..fc23f41b 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
package object chisel3 {
import scala.language.experimental.macros
@@ -5,12 +7,15 @@ package object chisel3 {
import internal.sourceinfo.{SourceInfo, SourceInfoTransform}
import util.BitPat
+ import chisel3.core.{Binding, FlippedBinder}
+ import chisel3.util._
+ import chisel3.internal.firrtl.Port
type Direction = chisel3.core.Direction
- val INPUT = chisel3.core.INPUT
- val OUTPUT = chisel3.core.OUTPUT
- val NO_DIR = chisel3.core.NO_DIR
- type Flipped = chisel3.core.Flipped
+ val Input = chisel3.core.Input
+ val Output = chisel3.core.Output
+ val Flipped = chisel3.core.Flipped
+
type Data = chisel3.core.Data
val Wire = chisel3.core.Wire
val Clock = chisel3.core.Clock
@@ -54,14 +59,37 @@ package object chisel3 {
val when = chisel3.core.when
type WhenContext = chisel3.core.WhenContext
+ /**
+ * These implicit classes allow one to convert scala.Int|scala.BigInt to
+ * Chisel.UInt|Chisel.SInt by calling .asUInt|.asSInt on them, respectively.
+ * The versions .asUInt(width)|.asSInt(width) are also available to explicitly
+ * mark a width for the new literal.
+ *
+ * Also provides .asBool to scala.Boolean and .asUInt to String
+ *
+ * Note that, for stylistic reasons, one should avoid extracting immediately
+ * after this call using apply, ie. 0.asUInt(1)(0) due to potential for
+ * confusion (the 1 is a bit length and the 0 is a bit extraction position).
+ * Prefer storing the result and then extracting from it.
+ */
+ implicit class fromIntToLiteral(val x: Int) extends AnyVal {
+ def U: UInt = UInt(BigInt(x), Width())
+ def S: SInt = SInt(BigInt(x), Width())
+ def asUInt() = UInt(x, Width())
+ def asSInt() = SInt(x, Width())
+ def asUInt(width: Int) = UInt(x, width)
+ def asSInt(width: Int) = SInt(x, width)
+ }
+
implicit class fromBigIntToLiteral(val x: BigInt) extends AnyVal {
def U: UInt = UInt(x, Width())
def S: SInt = SInt(x, Width())
- }
- implicit class fromIntToLiteral(val x: Int) extends AnyVal {
- def U: UInt = UInt(BigInt(x), Width())
- def S: SInt = SInt(BigInt(x), Width())
+
+ def asUInt() = UInt(x, Width())
+ def asSInt() = SInt(x, Width())
+ def asUInt(width: Int) = UInt(x, width)
+ def asSInt(width: Int) = SInt(x, width)
}
implicit class fromStringToLiteral(val x: String) extends AnyVal {
def U: UInt = UInt(x)
@@ -79,4 +107,39 @@ package object chisel3 {
def do_!= (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that != x
def do_=/= (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that =/= x
}
+
+ // Compatibility with existing code.
+ val INPUT = chisel3.core.Direction.Input
+ val OUTPUT = chisel3.core.Direction.Output
+ val NODIR = chisel3.core.Direction.Unspecified
+ type ChiselException = chisel3.internal.ChiselException
+ type ValidIO[+T <: Data] = chisel3.util.Valid[T]
+ val ValidIO = chisel3.util.Valid
+ val Decoupled = chisel3.util.DecoupledIO
+
+ class EnqIO[+T <: Data](gen: T) extends DecoupledIO(gen) {
+ def init(): Unit = {
+ this.noenq()
+ }
+ override def cloneType: this.type = EnqIO(gen).asInstanceOf[this.type]
+ }
+ class DeqIO[+T <: Data](gen: T) extends DecoupledIO(gen) {
+ Binding.bind(this, FlippedBinder, "Error: Cannot flip ")
+ def init(): Unit = {
+ this.nodeq()
+ }
+ override def cloneType: this.type = DeqIO(gen).asInstanceOf[this.type]
+ }
+ object EnqIO {
+ def apply[T<:Data](gen: T): EnqIO[T] = new EnqIO(gen)
+ }
+ object DeqIO {
+ def apply[T<:Data](gen: T): DeqIO[T] = new DeqIO(gen)
+ }
+
+ // Debugger/Tester access to internal Chisel data structures and methods.
+ def getDataElements(a: Aggregate): Seq[Element] = {
+ a.allElements
+ }
+ def getModulePorts(m: Module): Seq[Port] = m.getPorts
}
diff --git a/src/main/scala/chisel3/testers/BasicTester.scala b/src/main/scala/chisel3/testers/BasicTester.scala
index f91536d5..329237c6 100644
--- a/src/main/scala/chisel3/testers/BasicTester.scala
+++ b/src/main/scala/chisel3/testers/BasicTester.scala
@@ -12,7 +12,7 @@ import internal.sourceinfo.SourceInfo
class BasicTester extends Module {
// The testbench has no IOs, rather it should communicate using printf, assert, and stop.
- val io = new Bundle()
+ val io = IO(new Bundle())
def popCount(n: Long): Int = n.toBinaryString.count(_=='1')
diff --git a/src/main/scala/chisel3/util/Arbiter.scala b/src/main/scala/chisel3/util/Arbiter.scala
index eb541977..5875b3f2 100644
--- a/src/main/scala/chisel3/util/Arbiter.scala
+++ b/src/main/scala/chisel3/util/Arbiter.scala
@@ -9,9 +9,9 @@ import chisel3._
/** An I/O bundle for the Arbiter */
class ArbiterIO[T <: Data](gen: T, n: Int) extends Bundle {
- val in = Vec(n, Decoupled(gen)).flip
- val out = Decoupled(gen)
- val chosen = UInt(OUTPUT, log2Up(n))
+ val in = Flipped(Vec(n, DecoupledIO(gen)))
+ val out = DecoupledIO(gen)
+ val chosen = Output(UInt.width(log2Up(n)))
}
/** Arbiter Control determining which producer has access */
@@ -27,7 +27,7 @@ private object ArbiterCtrl
abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool]) extends Module {
def grant: Seq[Bool]
def choice: UInt
- val io = new ArbiterIO(gen, n)
+ val io = IO(new ArbiterIO(gen, n))
io.chosen := choice
io.out.valid := io.in(io.chosen).valid
@@ -101,7 +101,7 @@ class RRArbiter[T <: Data](gen:T, n: Int) extends LockingRRArbiter[T](gen, n, 1)
consumer.io.in <> arb.io.out
*/
class Arbiter[T <: Data](gen: T, n: Int) extends Module {
- val io = new ArbiterIO(gen, n)
+ val io = IO(new ArbiterIO(gen, n))
io.chosen := UInt(n-1)
io.out.bits := io.in(n-1).bits
diff --git a/src/main/scala/chisel3/util/BitPat.scala b/src/main/scala/chisel3/util/BitPat.scala
index 26106080..e79b882b 100644
--- a/src/main/scala/chisel3/util/BitPat.scala
+++ b/src/main/scala/chisel3/util/BitPat.scala
@@ -76,7 +76,7 @@ object BitPat {
// TODO: Break out of Core? (this doesn't involve FIRRTL generation)
/** Bit patterns are literals with masks, used to represent values with don't
* cares. Equality comparisons will ignore don't care bits (for example,
- * BitPat(0b10?1) === UInt(0b1001) and UInt(0b1011)).
+ * BitPat(0b10?1) === 0b1001.asUInt and 0b1011.asUInt.
*/
sealed class BitPat(val value: BigInt, val mask: BigInt, width: Int) {
def getWidth: Int = width
@@ -84,7 +84,7 @@ sealed class BitPat(val value: BigInt, val mask: BigInt, width: Int) {
def =/= (that: UInt): Bool = macro SourceInfoTransform.thatArg
def != (that: UInt): Bool = macro SourceInfoTransform.thatArg
- def do_=== (that: UInt)(implicit sourceInfo: SourceInfo): Bool = UInt(value, width) === (that & UInt(mask))
+ def do_=== (that: UInt)(implicit sourceInfo: SourceInfo): Bool = value.asUInt === (that & mask.asUInt)
def do_=/= (that: UInt)(implicit sourceInfo: SourceInfo): Bool = !(this === that)
def do_!= (that: UInt)(implicit sourceInfo: SourceInfo): Bool = this =/= that
}
diff --git a/src/main/scala/chisel3/util/Bitwise.scala b/src/main/scala/chisel3/util/Bitwise.scala
index 6451ab14..1d48ec0a 100644
--- a/src/main/scala/chisel3/util/Bitwise.scala
+++ b/src/main/scala/chisel3/util/Bitwise.scala
@@ -27,7 +27,7 @@ object Fill {
/** Fan out x n times */
def apply(n: Int, x: UInt): UInt = {
n match {
- case 0 => UInt(width=0)
+ case 0 => UInt.width(0)
case 1 => x
case _ if x.isWidthKnown && x.getWidth == 1 =>
Mux(x.toBool, UInt((BigInt(1) << n) - 1, n), UInt(0, n))
diff --git a/src/main/scala/chisel3/util/CircuitMath.scala b/src/main/scala/chisel3/util/CircuitMath.scala
index a64447d9..c809e14b 100644
--- a/src/main/scala/chisel3/util/CircuitMath.scala
+++ b/src/main/scala/chisel3/util/CircuitMath.scala
@@ -10,7 +10,7 @@ import chisel3._
/** Compute the base-2 integer logarithm of a UInt
* @example
* {{{ data_out := Log2(data_in) }}}
- * @note The result is truncated, so e.g. Log2(UInt(13)) = 3
+ * @note The result is truncated, so e.g. Log2(13.U) = 3
*/
object Log2 {
/** Compute the Log2 on the least significant n bits of x */
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index f37a5c31..0d000f49 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -10,71 +10,64 @@ import chisel3._
/** An I/O Bundle with simple handshaking using valid and ready signals for data 'bits'*/
class DecoupledIO[+T <: Data](gen: T) extends Bundle
{
- val ready = Bool(INPUT)
- val valid = Bool(OUTPUT)
- val bits = gen.cloneType.asOutput
- def fire(dummy: Int = 0): Bool = ready && valid
- override def cloneType: this.type = new DecoupledIO(gen).asInstanceOf[this.type]
+ val ready = Input(Bool())
+ val valid = Output(Bool())
+ val bits = Output(gen.chiselCloneType)
+ override def cloneType: this.type = DecoupledIO(gen).asInstanceOf[this.type]
}
-/** Adds a ready-valid handshaking protocol to any interface.
- * The standard used is that the consumer uses the flipped interface.
- */
-object Decoupled {
+object DecoupledIO {
+ /** Adds a ready-valid handshaking protocol to any interface.
+ * The standard used is that the consumer uses the flipped interface.
+ */
def apply[T <: Data](gen: T): DecoupledIO[T] = new DecoupledIO(gen)
-}
-/** An I/O bundle for enqueuing data with valid/ready handshaking
- * Initialization must be handled, if necessary, by the parent circuit
- */
-class EnqIO[T <: Data](gen: T) extends DecoupledIO(gen)
-{
- /** push dat onto the output bits of this interface to let the consumer know it has happened.
- * @param dat the values to assign to bits.
- * @return dat.
- */
- def enq(dat: T): T = { valid := Bool(true); bits := dat; dat }
+ implicit class AddMethodsToDecoupled[T<:Data](val target: DecoupledIO[T]) extends AnyVal {
+ def fire(): Bool = target.ready && target.valid
+
+ /** push dat onto the output bits of this interface to let the consumer know it has happened.
+ * @param dat the values to assign to bits.
+ * @return dat.
+ */
+ def enq(dat: T): T = {
+ target.valid := Bool(true)
+ target.bits := dat
+ dat
+ }
- /** Initialize this Bundle. Valid is set to false, and all bits are set to zero.
- * NOTE: This method of initialization is still being discussed and could change in the
- * future.
- */
- def init(): Unit = {
- valid := Bool(false)
- for (io <- bits.flatten)
- io := UInt(0)
- }
- override def cloneType: this.type = { new EnqIO(gen).asInstanceOf[this.type]; }
-}
+ /** Indicate no enqueue occurs. Valid is set to false, and all bits are set to zero.
+ */
+ def noenq(): Unit = {
+ target.valid := Bool(false)
+ target.bits := target.bits.fromBits(0.asUInt)
+ }
-/** An I/O bundle for dequeuing data with valid/ready handshaking.
- * Initialization must be handled, if necessary, by the parent circuit
- */
-class DeqIO[T <: Data](gen: T) extends DecoupledIO(gen) with Flipped
-{
- /** Assert ready on this port and return the associated data bits.
- * This is typically used when valid has been asserted by the producer side.
- * @param b ignored
- * @return the data for this device,
- */
- def deq(b: Boolean = false): T = { ready := Bool(true); bits }
+ /** Assert ready on this port and return the associated data bits.
+ * This is typically used when valid has been asserted by the producer side.
+ * @param b ignored
+ * @return the data for this device,
+ */
+ def deq(): T = {
+ target.ready := Bool(true)
+ target.bits
+ }
- /** Initialize this Bundle.
- * NOTE: This method of initialization is still being discussed and could change in the
- * future.
- */
- def init(): Unit = {
- ready := Bool(false)
+ /** Indicate no dequeue occurs. Ready is set to false
+ */
+ def nodeq(): Unit = {
+ target.ready := Bool(false)
+ }
}
- override def cloneType: this.type = { new DeqIO(gen).asInstanceOf[this.type]; }
+// override def cloneType: this.type = {
+// DeqIO(gen).asInstanceOf[this.type]
+// }
}
-/** An I/O bundle for dequeuing data with valid/ready handshaking */
-class DecoupledIOC[+T <: Data](gen: T) extends Bundle
-{
- val ready = Bool(INPUT)
- val valid = Bool(OUTPUT)
- val bits = gen.cloneType.asOutput
+object EnqIO {
+ def apply[T<:Data](gen: T): DecoupledIO[T] = DecoupledIO(gen)
+}
+object DeqIO {
+ def apply[T<:Data](gen: T): DecoupledIO[T] = Flipped(DecoupledIO(gen))
}
/** An I/O Bundle for Queues
@@ -83,11 +76,11 @@ class DecoupledIOC[+T <: Data](gen: T) extends Bundle
class QueueIO[T <: Data](gen: T, entries: Int) extends Bundle
{
/** I/O to enqueue data, is [[Chisel.DecoupledIO]] flipped */
- val enq = Decoupled(gen.cloneType).flip()
+ val enq = DeqIO(gen)
/** I/O to enqueue data, is [[Chisel.DecoupledIO]]*/
- val deq = Decoupled(gen.cloneType)
+ val deq = EnqIO(gen)
/** The current amount of data in the queue */
- val count = UInt(OUTPUT, log2Up(entries + 1))
+ val count = Output(UInt.width(log2Up(entries + 1)))
}
/** A hardware module implementing a Queue
@@ -110,8 +103,8 @@ class Queue[T <: Data](gen: T, val entries: Int,
extends Module(override_reset=override_reset) {
def this(gen: T, entries: Int, pipe: Boolean, flow: Boolean, _reset: Bool) =
this(gen, entries, pipe, flow, Some(_reset))
-
- val io = new QueueIO(gen, entries)
+
+ val io = IO(new QueueIO(gen, entries))
val ram = Mem(entries, gen)
val enq_ptr = Counter(entries)
@@ -169,14 +162,14 @@ extends Module(override_reset=override_reset) {
from the inputs.
Example usage:
- {{{ val q = Queue(Decoupled(UInt()), 16)
+ {{{ val q = Queue(DecoupledIO(UInt()), 16)
q.io.enq <> producer.io.out
consumer.io.in <> q.io.deq }}}
*/
object Queue
{
def apply[T <: Data](enq: DecoupledIO[T], entries: Int = 2, pipe: Boolean = false): DecoupledIO[T] = {
- val q = Module(new Queue(enq.bits.cloneType, entries, pipe))
+ val q = Module(new Queue(enq.bits.chiselCloneType, entries, pipe))
q.io.enq.valid := enq.valid // not using <> so that override is allowed
q.io.enq.bits := enq.bits
enq.ready := q.io.enq.ready
diff --git a/src/main/scala/chisel3/util/Reg.scala b/src/main/scala/chisel3/util/Reg.scala
index 81de4754..37c28b14 100644
--- a/src/main/scala/chisel3/util/Reg.scala
+++ b/src/main/scala/chisel3/util/Reg.scala
@@ -25,7 +25,8 @@ object RegInit {
object RegEnable
{
def apply[T <: Data](updateData: T, enable: Bool): T = {
- val r = Reg(updateData)
+ val clonedUpdateData = updateData.chiselCloneType
+ val r = Reg(clonedUpdateData)
when (enable) { r := updateData }
r
}
diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala
index 78187ff6..743038f3 100644
--- a/src/main/scala/chisel3/util/Valid.scala
+++ b/src/main/scala/chisel3/util/Valid.scala
@@ -7,20 +7,18 @@ package chisel3.util
import chisel3._
-/** An I/O Bundle containing data and a signal determining if it is valid */
-class ValidIO[+T <: Data](gen2: T) extends Bundle
+/** An Bundle containing data and a signal determining if it is valid */
+class Valid[+T <: Data](gen: T) extends Bundle
{
- val valid = Bool(OUTPUT)
- val bits = gen2.cloneType.asOutput
+ val valid = Output(Bool())
+ val bits = Output(gen.chiselCloneType)
def fire(dummy: Int = 0): Bool = valid
- override def cloneType: this.type = new ValidIO(gen2).asInstanceOf[this.type]
+ override def cloneType: this.type = Valid(gen).asInstanceOf[this.type]
}
-/** Adds a valid protocol to any interface. The standard used is
- that the consumer uses the flipped interface.
-*/
+/** Adds a valid protocol to any interface */
object Valid {
- def apply[T <: Data](gen: T): ValidIO[T] = new ValidIO(gen)
+ def apply[T <: Data](gen: T): Valid[T] = new Valid(gen)
}
/** A hardware module that delays data coming down the pipeline
@@ -34,7 +32,7 @@ object Valid {
*/
object Pipe
{
- def apply[T <: Data](enqValid: Bool, enqBits: T, latency: Int): ValidIO[T] = {
+ def apply[T <: Data](enqValid: Bool, enqBits: T, latency: Int): Valid[T] = {
if (latency == 0) {
val out = Wire(Valid(enqBits))
out.valid <> enqValid
@@ -46,16 +44,16 @@ object Pipe
apply(v, b, latency-1)
}
}
- def apply[T <: Data](enqValid: Bool, enqBits: T): ValidIO[T] = apply(enqValid, enqBits, 1)
- def apply[T <: Data](enq: ValidIO[T], latency: Int = 1): ValidIO[T] = apply(enq.valid, enq.bits, latency)
+ def apply[T <: Data](enqValid: Bool, enqBits: T): Valid[T] = apply(enqValid, enqBits, 1)
+ def apply[T <: Data](enq: Valid[T], latency: Int = 1): Valid[T] = apply(enq.valid, enq.bits, latency)
}
class Pipe[T <: Data](gen: T, latency: Int = 1) extends Module
{
- val io = new Bundle {
- val enq = Valid(gen).flip
- val deq = Valid(gen)
- }
+ val io = IO(new Bundle {
+ val enq = Input(Valid(gen))
+ val deq = Output(Valid(gen))
+ })
io.deq <> Pipe(io.enq, latency)
}
generated by cgit v1.2.3 (git 2.25.1) at 2026-02-01 16:50:16 +0000