summaryrefslogtreecommitdiff
path: root/src/main
diff options
context:
space:
mode:
Diffstat (limited to 'src/main')
-rw-r--r--src/main/scala/chisel3/compatibility.scala48
-rw-r--r--src/main/scala/chisel3/package.scala40
-rw-r--r--src/main/scala/chisel3/util/Counter.scala2
-rw-r--r--src/main/scala/chisel3/util/Decoupled.scala2
-rw-r--r--src/main/scala/chisel3/util/LFSR.scala2
-rw-r--r--src/main/scala/chisel3/util/Reg.scala34
-rw-r--r--src/main/scala/chisel3/util/Valid.scala2
7 files changed, 95 insertions, 35 deletions
diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index aee02dfe..17fd1fee 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -165,7 +165,51 @@ package object Chisel { // scalastyle:ignore package.object.name
val printf = chisel3.core.printf
- val Reg = chisel3.core.Reg
+ val RegNext = chisel3.core.RegNext
+ val RegInit = chisel3.core.RegInit
+ object Reg {
+ import chisel3.core.{Binding, CompileOptions}
+ import chisel3.internal.sourceinfo.SourceInfo
+
+ /** Creates a register with optional next and initialization values.
+ *
+ * @param t: data type for the register
+ * @param next: new value register is to be updated with every cycle (or
+ * empty to not update unless assigned to using the := operator)
+ * @param init: initialization value on reset (or empty for uninitialized,
+ * where the register value persists across a reset)
+ *
+ * @note this may result in a type error if called from a type parameterized
+ * function, since the Scala compiler isn't smart enough to know that null
+ * is a valid value. In those cases, you can either use the outType only Reg
+ * constructor or pass in `null.asInstanceOf[T]`.
+ */
+ def apply[T <: Data](t: T = null, next: T = null, init: T = null)
+ (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = {
+ if (t ne null) {
+ val reg = if (init ne null) {
+ RegInit(t, init)
+ } else {
+ chisel3.core.Reg(t)
+ }
+ if (next ne null) {
+ Binding.checkSynthesizable(next, s"'next' ($next)") // TODO: move into connect?
+ reg := next
+ }
+ reg
+ } else if (next ne null) {
+ if (init ne null) {
+ RegNext(next, init)
+ } else {
+ RegNext(next)
+ }
+ } else if (init ne null) {
+ RegInit(init)
+ } else {
+ throwException("cannot infer type")
+ }
+ }
+ }
val when = chisel3.core.when
type WhenContext = chisel3.core.WhenContext
@@ -340,8 +384,6 @@ package object Chisel { // scalastyle:ignore package.object.name
val UIntToOH = chisel3.util.UIntToOH
val PriorityEncoderOH = chisel3.util.PriorityEncoderOH
- val RegNext = chisel3.util.RegNext
- val RegInit = chisel3.util.RegInit
val RegEnable = chisel3.util.RegEnable
val ShiftRegister = chisel3.util.ShiftRegister
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 0ccdfc29..191b636e 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -155,7 +155,45 @@ package object chisel3 { // scalastyle:ignore package.object.name
val printf = chisel3.core.printf
- val Reg = chisel3.core.Reg
+ val RegNext = chisel3.core.RegNext
+ val RegInit = chisel3.core.RegInit
+ object Reg {
+ import chisel3.core.{Binding, CompileOptions}
+ import chisel3.internal.sourceinfo.SourceInfo
+ import chisel3.internal.throwException
+
+ // Passthrough for chisel3.core.Reg
+ // TODO: make val Reg = chisel3.core.Reg once we eliminate the legacy Reg constructor
+ def apply[T <: Data](t: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T =
+ chisel3.core.Reg(t)
+
+ @deprecated("Use Reg(t), RegNext(next, [init]) or RegInit([t], init) instead", "chisel3")
+ def apply[T <: Data](t: T = null, next: T = null, init: T = null)
+ (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = {
+ if (t ne null) {
+ val reg = if (init ne null) {
+ RegInit(t, init)
+ } else {
+ chisel3.core.Reg(t)
+ }
+ if (next ne null) {
+ Binding.checkSynthesizable(next, s"'next' ($next)") // TODO: move into connect?
+ reg := next
+ }
+ reg
+ } else if (next ne null) {
+ if (init ne null) {
+ RegNext(next, init)
+ } else {
+ RegNext(next)
+ }
+ } else if (init ne null) {
+ RegInit(init)
+ } else {
+ throwException("cannot infer type")
+ }
+ }
+ }
val when = chisel3.core.when
type WhenContext = chisel3.core.WhenContext
diff --git a/src/main/scala/chisel3/util/Counter.scala b/src/main/scala/chisel3/util/Counter.scala
index 6e533ea6..aa0c0d43 100644
--- a/src/main/scala/chisel3/util/Counter.scala
+++ b/src/main/scala/chisel3/util/Counter.scala
@@ -14,7 +14,7 @@ import chisel3.internal.naming.chiselName // can't use chisel3_ version because
@chiselName
class Counter(val n: Int) {
require(n >= 0)
- val value = if (n > 1) Reg(init=0.U(log2Ceil(n).W)) else 0.U
+ val value = if (n > 1) RegInit(0.U(log2Ceil(n).W)) else 0.U
/** Increment the counter, returning whether the counter currently is at the
* maximum and will wrap. The incremented value is registered and will be
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index 815a507b..67da6a17 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -182,7 +182,7 @@ extends Module(override_reset=override_reset) {
private val ram = Mem(entries, gen)
private val enq_ptr = Counter(entries)
private val deq_ptr = Counter(entries)
- private val maybe_full = Reg(init=false.B)
+ private val maybe_full = RegInit(false.B)
private val ptr_match = enq_ptr.value === deq_ptr.value
private val empty = ptr_match && !maybe_full
diff --git a/src/main/scala/chisel3/util/LFSR.scala b/src/main/scala/chisel3/util/LFSR.scala
index 94c340c4..ff2bf840 100644
--- a/src/main/scala/chisel3/util/LFSR.scala
+++ b/src/main/scala/chisel3/util/LFSR.scala
@@ -19,7 +19,7 @@ object LFSR16 {
@chiselName
def apply(increment: Bool = true.B): UInt = {
val width = 16
- val lfsr = Reg(init=1.U(width.W))
+ val lfsr = RegInit(1.U(width.W))
when (increment) { lfsr := Cat(lfsr(0)^lfsr(2)^lfsr(3)^lfsr(5), lfsr(width-1,1)) }
lfsr
}
diff --git a/src/main/scala/chisel3/util/Reg.scala b/src/main/scala/chisel3/util/Reg.scala
index 27785dfb..e85a02fb 100644
--- a/src/main/scala/chisel3/util/Reg.scala
+++ b/src/main/scala/chisel3/util/Reg.scala
@@ -6,41 +6,21 @@ import chisel3._
// TODO: remove this once we have CompileOptions threaded through the macro system.
import chisel3.core.ExplicitCompileOptions.NotStrict
-object RegNext {
- /** Returns a register with the specified next and no reset initialization.
- *
- * Essentially a 1-cycle delayed version of the input signal.
- */
- def apply[T <: Data](next: T): T = Reg[T](null.asInstanceOf[T], next, null.asInstanceOf[T])
-
- /** Returns a register with the specified next and reset initialization.
- *
- * Essentially a 1-cycle delayed version of the input signal.
- */
- def apply[T <: Data](next: T, init: T): T = Reg[T](null.asInstanceOf[T], next, init)
-}
-
-object RegInit {
- /** Returns a register pre-initialized (on reset) to the specified value.
- */
- def apply[T <: Data](init: T): T = Reg[T](null.asInstanceOf[T], null.asInstanceOf[T], init)
-}
-
object RegEnable {
/** Returns a register with the specified next, update enable gate, and no reset initialization.
*/
- def apply[T <: Data](updateData: T, enable: Bool): T = {
- val clonedUpdateData = updateData.chiselCloneType
- val r = Reg(clonedUpdateData)
- when (enable) { r := updateData }
+ def apply[T <: Data](next: T, enable: Bool): T = {
+ val clonedNext = next.chiselCloneType
+ val r = Reg(clonedNext)
+ when (enable) { r := next }
r
}
/** Returns a register with the specified next, update enable gate, and reset initialization.
*/
- def apply[T <: Data](updateData: T, resetData: T, enable: Bool): T = {
- val r = RegInit(resetData)
- when (enable) { r := updateData }
+ def apply[T <: Data](next: T, init: T, enable: Bool): T = {
+ val r = RegInit(init)
+ when (enable) { r := next }
r
}
}
diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala
index 0bfe7cb3..000fff97 100644
--- a/src/main/scala/chisel3/util/Valid.scala
+++ b/src/main/scala/chisel3/util/Valid.scala
@@ -44,7 +44,7 @@ object Pipe
out.bits <> enqBits
out
} else {
- val v = Reg(Bool(), next=enqValid, init=false.B)
+ val v = RegNext(enqValid, false.B)
val b = RegEnable(enqBits, enqValid)
apply(v, b, latency-1)
}
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-31 21:34:38 +0000