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Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/chisel3/stage/ChiselStage.scala | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/stage/ChiselStage.scala b/src/main/scala/chisel3/stage/ChiselStage.scala index 938f0250..ec53757f 100644 --- a/src/main/scala/chisel3/stage/ChiselStage.scala +++ b/src/main/scala/chisel3/stage/ChiselStage.scala @@ -73,7 +73,7 @@ class ChiselStage extends Stage with PreservesAll[Phase] { * @param gen a call-by-name Chisel module * @param args additional command line arguments to pass to Chisel * param annotations additional annotations to pass to Chisel - * @return a string containing the Verilog output + * @return a string containing the FIRRTL output */ final def emitFirrtl( gen: => RawModule, @@ -108,6 +108,24 @@ class ChiselStage extends Stage with PreservesAll[Phase] { .value } + /** Convert a Chisel module to SystemVerilog + * @param gen a call-by-name Chisel module + * @param args additional command line arguments to pass to Chisel + * param annotations additional annotations to pass to Chisel + * @return a string containing the SystemVerilog output + */ + final def emitSystemVerilog( + gen: => RawModule, + args: Array[String] = Array.empty, + annotations: AnnotationSeq = Seq.empty): String = { + + execute(Array("-X", "sverilog") ++ args, ChiselGeneratorAnnotation(() => gen) +: annotations) + .collectFirst { + case DeletedAnnotation(_, EmittedVerilogCircuitAnnotation(a)) => a + } + .get + .value + } } object ChiselMain extends StageMain(new ChiselStage) |