1 files changed, 16 insertions, 0 deletions
diff --git a/src/main/scala/chisel3/util/Reg.scala b/src/main/scala/chisel3/util/Reg.scala
index 00005e3a..27785dfb 100644
--- a/src/main/scala/chisel3/util/Reg.scala
+++ b/src/main/scala/chisel3/util/Reg.scala
@@ -61,4 +61,20 @@ object ShiftRegister
       in
     }
   }
+
+  /** Returns the n-cycle delayed version of the input signal with reset initialization.
+    *
+    * @param in input to delay
+    * @param n number of cycles to delay
+    * @param resetData reset value for each register in the shift
+    * @param en enable the shift
+    */
+  def apply[T <: Data](in: T, n: Int, resetData: T, en: Bool): T = {
+    // The order of tests reflects the expected use cases.
+    if (n != 0) {
+      RegEnable(apply(in, n-1, resetData, en), resetData, en)
+    } else {
+      in
+    }
+  }
 }